Integrated circuit device

An integrated circuit device, comprising:

• a front-end-of-line (FEOL) structure including a substrate, a plurality of integrated devices, and a lower insulating layer on the substrate;
• a first wiring structure on the FEOL structure, the first wiring structure extending in a first direction parallel to an upper surface of the substrate;
• a second wiring structure spaced apart from the first wiring structure in a second direction perpendicular to the first direction;
• a via layer on the first wiring structure and connected to the first wiring structure;
• and
• an interlayer insulating layer between the first wiring structure and the second wiring structure,
• wherein:
• the first wiring structure includes:
• a first wiring layer directly on an upper surface of the FEOL structure and extending continuously in a vertical direction, perpendicular to the upper surface of the substrate, from an upper surface of the FEOL structure to an upper surface of the first wiring layer, and
• an insulating pattern surrounding a sidewall of the first wiring layer and including a first insulating material, the insulating pattern including a portion extending continuously in the vertical direction from the upper surface of the FEOL structure to an upper surface of the insulating pattern, and
• the interlayer insulating layer covers a sidewall of the insulating pattern between the first wiring structure and the second wiring structure and has an upper surface higher than the upper surface of the first wiring layer and the upper surface of the insulating pattern,
• the portion of the insulating pattern of the first wiring structure has a constant width in the second direction perpendicular to the first direction and perpendicular to the vertical direction.

An integrated circuit device, comprising:

• a front-end-of-line (FEOL) structure including a substrate, a plurality of integrated devices, and a lower insulating layer on the substrate;
• a plurality of wiring structures on the FEOL structure, the plurality of wiring structures extending in a first direction parallel to an upper surface of the substrate and each including:
• a wiring layer directly on an upper surface of the FEOL structure and extending continuously in a vertical direction, perpendicular to the upper surface of the substrate, from the upper surface of the FEOL structure to an upper surface of the wiring layer,
• an insulating pattern surrounding a sidewall of the wiring layer and including a first insulating material, the insulating pattern including a portion extending continuously in the vertical direction from the upper surface of the FEOL structure to an upper surface of the insulating pattern, and
• a capping layer on the upper surface of the wiring layer and including a conductive material,
• a via layer on and connected to a first wiring structure of the plurality of wiring structures;
• and
• an interlayer insulating layer covering a sidewall of the insulating pattern between each wiring structure of the plurality of wiring structures, the interlayer insulating layer having an upper surface higher than the upper surface of each wiring layer and higher than the upper surface of each insulating pattern,
• wherein:
• each capping layer has a height in the vertical direction that is less than a height of each wiring layer and is less than a height of the via layer,
• the upper surface of each insulating pattern is at a vertical level lower than an upper surface of each capping layer,
• each insulating pattern has a constant thickness along the sidewall of each wiring layer,
• the via layer includes:
• a first portion having a width in a second direction perpendicular to the first direction and perpendicular to the vertical direction that is less than a width of the first wiring structure, and
• a second portion on the first portion, the second portion having a width in the second direction that is greater than the width of the first wiring structure in the second direction,
• the first insulating material includes SiO2, Al2O3, or a combination thereof, and
• the conductive material includes graphene, Ti, Al, Cr, Au, Ni, Pt, or a combination thereof.