# US 12,765,358 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,358 B2 - Document ID: US12765358B2 - Status: Granted - Kind: B2 - Application number: 18/641,525 - Filed: 2024-04-22 - Published: 2025-05-29 - Granted: 2026-10-13 - Earliest claimed: 2023-11-28 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jung Han Lee; Jisoo Park; Byung-Sung Kim; Kwanyoung Chun - Web page: https://patentgrep.com/patent/US12765358B2 ## CPC - H10W 20/427: {Power or ground buses} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/6729: {characterised by the electrodes} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/121: {oriented parallel to substrates} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} - H10D 88/00: Three-dimensional [3D] integrated devices - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Disclosed is a semiconductor device comprising a first upper power line and a second upper power line extending in a first direction and are spaced apart from each other in a second direction intersecting the first direction, a first semiconductor pattern, a second semiconductor pattern spaced apart in the second direction from the first semiconductor pattern, a third semiconductor pattern spaced apart in the second direction from the second semiconductor pattern, a fourth semiconductor pattern spaced apart in the first direction from the first semiconductor pattern, and a fifth semiconductor pattern spaced apart in the first direction from the third semiconductor pattern. The first to fifth semiconductor patterns are between the first upper power line and the second upper power line. The second semiconductor pattern is between the first semiconductor pattern and the third semiconductor pattern. ## Claims ### Claim 1 A semiconductor device, comprising: a first upper power line and a second upper power line extending in a first direction and are spaced apart from each other in a second direction intersecting the first direction; a first semiconductor pattern; a second semiconductor pattern spaced apart in the second direction from the first semiconductor pattern; a third semiconductor pattern spaced apart in the second direction from the second semiconductor pattern; a fourth semiconductor pattern spaced apart in the first direction from the first semiconductor pattern; and a fifth semiconductor pattern spaced apart in the first direction from the third semiconductor pattern, wherein the first to fifth semiconductor patterns are between the first upper power line and the second upper power line, wherein the second semiconductor pattern is between the first semiconductor pattern and the third semiconductor pattern, and wherein a distance between the first semiconductor pattern and the third semiconductor pattern is greater than a distance between the fourth semiconductor pattern and the fifth semiconductor pattern. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein a width in the second direction of each of the first to third semiconductor patterns is less than a width in the second direction of each of the fourth and fifth semiconductor patterns. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the width in the second direction of each of the fourth and fifth semiconductor patterns is 1.5 times to 3 times the width in the second direction of each of the first to third semiconductor patterns. ### Claim 4 (depends on 1) The semiconductor device of claim 1, further comprising a third upper power line and a fourth upper power line between the first upper power line and the second upper power line, wherein the third upper power line overlaps the fourth semiconductor pattern, and wherein the fourth upper power line overlaps the fifth semiconductor pattern. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein each of the third and fourth upper power lines are not overlapping any of the first to third semiconductor patterns. ### Claim 6 (depends on 4) The semiconductor device of claim 4, wherein a width in the second direction of each of the first to third semiconductor patterns is less than a distance in the second direction between the third and fourth upper power lines. ### Claim 7 (depends on 4) The semiconductor device of claim 4, wherein a width in the second direction of each of the fourth and fifth semiconductor patterns is greater than a distance in the second direction between the third and fourth upper power lines. ### Claim 8 A semiconductor device, comprising: a first semiconductor pattern; a second semiconductor pattern and a third semiconductor pattern overlapping in a first direction with the first semiconductor pattern; a fourth semiconductor pattern overlapping in a second direction with the first semiconductor pattern, the second direction intersecting the first direction; and a fifth semiconductor pattern overlapping in the second direction with the third semiconductor pattern, wherein the second semiconductor pattern is between the first semiconductor pattern and the third semiconductor pattern, and wherein a width in the first direction of each of the first to third semiconductor patterns is less than a width in the first direction of each of the fourth and fifth semiconductor patterns. ### Claim 9 (depends on 8) The semiconductor device of claim 8, further comprising: a first source/drain structure contacting the first semiconductor pattern; a second source/drain structure contacting the second semiconductor pattern; a third source/drain structure contacting the third semiconductor pattern; a fourth source/drain structure contacting the fourth semiconductor pattern; and a fifth source/drain structure contacting the fifth semiconductor pattern, wherein each of the first to fifth source/drain structures includes an upper source/drain pattern and a lower source/drain pattern, wherein the lower source/drain pattern overlaps the upper source/drain pattern in a third direction, and wherein the third direction intersects the first direction and the second direction. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein a width in the first direction of each of the first to third source/drain structures is less than a width in the first direction of each of the fourth and fifth source/drain structures. ### Claim 11 (depends on 9) The semiconductor device of claim 9, further comprising: a first upper power line and a second upper power line extending in the second direction; an upper active contact contacting the upper source/drain pattern of the fourth source/drain structure; a first upper via connecting the upper active contact to the first upper power line; and a second upper via connecting the upper active contact to the second upper power line. ### Claim 12 (depends on 9) The semiconductor device of claim 9, further comprising: a first lower power line and a second lower power line extending in the second direction; a lower active contact contacting the lower source/drain pattern of the fourth source/drain structure; a first lower via connecting the lower active contact to the first lower power line; and a second lower via connecting the lower active contact to the second lower power line. ### Claim 13 (depends on 8) The semiconductor device of claim 8, further comprising: an upper electrode and a lower electrode overlapping the first semiconductor pattern; an upper gate contact contacting the upper electrode; a lower gate contact contacting the lower electrode; an upper signal line contacting the upper gate contact; and a lower signal line contacting the lower gate contact. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the upper electrode and the lower electrode include different conductive materials from each other. ### Claim 15 (depends on 8) The semiconductor device of claim 8, further comprising: a first gate electrode overlapping in a third direction with the first semiconductor pattern; a second gate electrode overlapping in the third direction with the second semiconductor pattern; a third gate electrode overlapping in the third direction with the third semiconductor pattern; a fourth gate electrode overlapping in the third direction with the fourth semiconductor pattern; and a fifth gate electrode overlapping in the third direction with the fifth semiconductor pattern, wherein the third direction intersects the first direction and the second direction, and wherein a width in the first direction of each of the first to third gate electrodes is less than a width in the first direction of each of the fourth and fifth gate electrodes. ### Claim 16 A semiconductor device, comprising: a first source/drain structure; a first semiconductor pattern contacting the first source/drain structure; a first gate electrode overlapping the first semiconductor pattern; a second source/drain structure spaced apart in a first direction from the first source/drain structure; a second semiconductor pattern contacting the second source/drain structure; a second gate electrode overlapping the second semiconductor pattern; a third source/drain structure spaced apart in the first direction from the second source/drain structure; a third semiconductor pattern contacting the third source/drain structure; a third gate electrode overlapping the third semiconductor pattern; a fourth source/drain structure spaced apart in a second direction from the first source/drain structure, the second direction intersecting the first direction; a fourth semiconductor pattern contacting the fourth source/drain structure; a fourth gate electrode overlapping the fourth semiconductor pattern; a fifth source/drain structure spaced apart in the second direction from the third source/drain structure; a fifth semiconductor pattern contacting the fifth source/drain structure; a fifth gate electrode overlapping the fifth semiconductor pattern; a first gate separation layer between the first gate electrode and the second gate electrode; a second gate separation layer between the second gate electrode and the third gate electrode; and a third gate separation layer between the fourth gate electrode and the fifth gate electrode, wherein each of the first to fifth source/drain structures includes an upper source/drain pattern and a lower source/drain pattern, and wherein the third gate separation layer is between the first gate separation layer and the second gate separation layer. ### Claim 17 (depends on 16) The semiconductor device of claim 16, further comprising: a first upper power line overlapping the first gate separation layer; and a second upper power line overlapping the second gate separation layer, wherein the third gate separation layer is between the first upper power line and the second upper power line. ### Claim 18 (depends on 17) The semiconductor device of claim 17, further comprising: a first lower power line overlapping the first gate separation layer; and a second lower power line overlapping the second gate separation layer, wherein the third gate separation layer is between the first lower power line and the second lower power line. ### Claim 19 (depends on 18) The semiconductor device of claim 18, further comprising: upper signal lines between the first upper power line and the second upper power line; and lower signal lines between the first lower power line and the second lower power line, wherein a number of the upper signal lines between the first upper power line and the second upper power line is greater than a number of the lower signal lines between the first lower power line and the second lower power line. ### Claim 20 (depends on 17) The semiconductor device of claim 17, further comprising a third upper power line and a fourth upper power line spaced apart in the first direction from each other across the first upper power line and the second upper power line, wherein the third upper power line includes a first part adjacent to the first semiconductor pattern and a second part adjacent to the fourth semiconductor pattern, and wherein a central line of the first part of the third upper power line and a central line of the second part of the third upper power line are on one straight line.