# US 12,765,356 B2 · Semiconductor device including power rail > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,356 B2 - Document ID: US12765356B2 - Status: Granted - Kind: B2 - Application number: 17/153,220 - Filed: 2021-01-20 - Published: 2022-02-03 - Granted: 2026-10-13 - Earliest claimed: 2020-07-30 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Woo Sick Choi - Web page: https://patentgrep.com/patent/US12765356B2 ## CPC - H10W 20/427: {Power or ground buses} - H10D 89/10: Integrated device layouts - H10W 20/43: Layouts of interconnections - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of the present disclosure relate to a semiconductor device. According to embodiments of the present disclosure, a semiconductor device may include: a first cell; a second cell; and a power rail that is a passage configured to supply power to the first cell, wherein the power rail may extend in a first direction, and wherein, in the power rail, a width in a second direction, of a portion overlapping the second cell may be greater than a width in the second direction, of a portion overlapping the first cell. This makes it possible to reduce power loss that occurs through the power rail in the semiconductor, and to reduce the possibility of an operation error of cells existing in the semiconductor device. ## Claims ### Claim 1 A semiconductor device comprising: a first cell; a second cell; a first power rail configured to supply power to the first cell, the first power rail being located on a first layer and the first power rail using the first layer with the first cell; and a second power rail configured to supply power to the first cell, the second power rail being located on a second layer and the second power rail using the second layer with the first cell; wherein the first power rail and the second power rail extend in a first direction, wherein the first power rail has a first section which is in direct contact with the first cell in the first direction and a second section which, along the first direction, is only in direct contact with the second cell, wherein a width of the second section in a second direction is greater than a width of the first section in the second direction, the second direction being perpendicular to the first direction, wherein the second power rail has a third section which is connected with the first cell in the first direction and a fourth section which is connected with the second cell in the first direction, wherein the first layer and the second layer are spaced apart from each other in a third direction perpendicular to the first direction and the second direction, wherein the first power rail and the second power rail are spaced apart from each other in the third direction, wherein the first cell is a standard cell, and the second cell is a filler cell or a decoupling capacitor cell, wherein the first power rail is expandable only in the second section, and wherein the width of the first power rail is uniform except the second section. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first cell uses a same layer with the first power rail. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first cell comprises at least one of a NOR gate, a NAND gate, a XOR gate, and an inverter. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein, in the first power rail, the width of the second section is greater than a set minimum width. ### Claim 5 A semiconductor device comprising: a first cell; a second cell; a first power rail configured to supply power to the first cell, the first power rail being located on a first layer and the first power rail using the first layer with the first cell; and a second power rail configured to supply power to the first cell, the second power rail being located on a second layer and the second power rail using the second layer with the first cell, wherein the first power rail and the second power rail extend in a first direction, wherein the first power rail has a first section which is in direct contact with the first cell in the first direction and a second section which, along the first direction, is only in direct contact with the second cell, wherein a width of the second section in a second direction is greater than a width of the first section in the second direction, the second direction being perpendicular to the first direction, wherein the second power rail has a third section which is connected with the first cell in the first direction and a fourth section which is connected with the second cell in the first direction, wherein a width of the third section in the second direction and a width of the fourth section in the second direction are uniform, wherein the first layer and the second layer are spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and wherein the first power rail and the second power rail are spaced apart from each other in the third direction, wherein the first cell is a standard cell, and the second cell is a filler cell or a decoupling capacitor cell, wherein the first power rail is expandable only in the second section, and wherein the width of the first power rail is uniform except the second section. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the first cell uses a same layer with the first power rail. ### Claim 7 (depends on 5) The semiconductor device of claim 5, wherein the first cell comprises at least one of a NOR gate, a NAND gate, a XOR gate, and an inverter. ### Claim 8 (depends on 5) The semiconductor device of claim 5, wherein, in the first power rail, the width of the second section is greater than a set minimum width. ### Claim 9 A semiconductor device comprising a first power rail configured to transfer power to at least one first cell, the first power rail having a line shape extending longitudinally along a first direction, the first power rail being located on a first layer and the first power rail using the first layer with the first cell, and a second power rail configured to transfer power to the first cell and a second cell, the second power rail having a line shape extending longitudinally along the first direction, the second power rail being located on a second layer, and the second power rail using the second layer with the first cell, wherein the first power rail has a first section which is in direct contact with the first cell in the first direction and a second section which, along the first direction, is only in direct contact with the second cell, wherein a width of the second section in a second direction is greater than a width of the first section in the second direction, the first direction being perpendicular to the second direction, wherein the second power rail has a third section which is connected with the first cell in the first direction and a fourth section which is connected with the second cell in the first direction, wherein the first power rail and the second power rail are spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and wherein the first cell is a standard cell, and the second cell is a filler cell or a decoupling capacitor cell, wherein the first power rail is expandable only in the second section, and wherein the width of the first power rail is uniform except the second section.