Fabrication methods of 3D semiconductor devices and structures with metal layers and connection path

A method to fabricate a semiconductor device, the method comprising:

• forming a first level, said first level comprising a single crystal silicon layer, a plurality of transistors, and a plurality of first metal layers,
• wherein each transistor of said plurality of transistors comprises a single crystal channel, and
• wherein said plurality of first metal layers comprise interconnections between said transistors of said plurality of transistors;
• thinning said single crystal silicon layer to a thickness of less than two microns;
• forming a second level, said second level comprising a plurality of second metal layers,
• wherein said second level is disposed underneath said first level;
• and
• forming a connection path between at least one of said transistors to at least one of said plurality of second metal layers,
• wherein said connective path comprises at least one via disposed through at least said single crystal silicon layer,
• wherein at least one of said transistors comprises a four-sided gate.

A method to fabricate a semiconductor device, the method comprising:

• forming a first level, said first level comprising a single crystal silicon layer, a plurality of transistors, and a plurality of first metal layers,
• wherein each transistor of said plurality of transistors comprises a single crystal channel, and
• wherein said plurality of first metal layers comprise interconnections between said transistors of said plurality of transistors;
• thinning said single crystal silicon layer to a thickness of less than two microns;
• forming a second level, said second level comprising a plurality of second metal layers,
• wherein said second level is disposed underneath said first level;
• and
• forming a connection path between at least one of said transistors to at least one of said second metal layers,
• wherein said connective path comprises at least one via disposed through at least said single crystal silicon layer,
• wherein said device comprises a plurality of capacitors, and
• wherein said second metal layers comprise Vdd supply lines and Vss supply lines,
• wherein at least one of said plurality of transistors comprises a first channel and a second channel, and
• wherein said second channel overlays said first channel.

A method to fabricate a semiconductor device, the method comprising:

• forming a first level, said first level comprising a single crystal silicon layer, a plurality of transistors, and a plurality of first metal layers,
• wherein each transistor of said plurality of transistors comprises a single crystal channel, and
• wherein said plurality of first metal layers comprise interconnections between said transistors of said plurality of transistors;
• thinning said single crystal silicon layer to a thickness of less than two microns;
• forming a second level, said second level comprising a plurality of second metal layers,
• wherein said second level is disposed underneath said first level;
• and
• forming a connection path between at least one of said transistors to at least one of said second metal layers,
• wherein said connective path comprises at least one via disposed through at least said single crystal silicon layer, and
• wherein at least one of said transistors comprises a four-sided gate.