# US 12,765,349 B2 · Semiconductor device structure including a vertical fuse structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,765,349 B2
- Document ID: US12765349B2
- Status: Granted
- Kind: B2
- Application number: 18/619,520
- Filed: 2024-03-28
- Published: 2025-10-02
- Granted: 2026-10-13
- Earliest claimed: 2024-03-28
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Jui-Hsiu Jao
- Web page: https://patentgrep.com/patent/US12765349B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive}
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure and a method of manufacturing the same are provided. The semiconductor device structure includes a semiconductor substrate, a fuse structure, and a circuit region. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The fuse structure is at least partially disposed within the semiconductor substrate. The circuit region is electrically connected to the fuse element. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium connecting the first fuse element and the second fuse element. The first fuse element, the second fuse element, and the fuse medium are arranged along a first direction from the first surface toward the second surface of the semiconductor substrate.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a semiconductor substrate having a first surface and a second surface opposite to the first surface;
a fuse structure at least partially disposed within the semiconductor substrate;
a circuit region electrically connected to the fuse structure,
a conductive via disposed over the second surface of the semiconductor substrate; and
a conductive layer disposed over the conductive via,
wherein the fuse structure comprises a first fuse element, a second fuse element, and a fuse medium connecting the first fuse element and the second fuse element, and wherein the first fuse element, the second fuse element, and the fuse medium are arranged along a first direction from the first surface toward the second surface of the semiconductor substrate;
wherein the circuit region is electrically connected to the fuse structure through the conductive via and the conductive layer;
wherein the fuse medium is located at an elevation substantially the same as that of the conductive via.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, wherein the first fuse element has a first surface exposed by the first surface of the semiconductor substrate.

### Claim 3 (depends on 2)

The semiconductor device structure of claim 2, wherein the first fuse element has a second surface, opposite to the first surface, exposed by the second surface of the semiconductor substrate.

### Claim 4 (depends on 2)

The semiconductor device structure of claim 2, wherein the second fuse element is disposed within the semiconductor substrate.

### Claim 5 (depends on 4)

The semiconductor device structure of claim 4, wherein the second fuse element has a surface exposed by the second surface of the semiconductor substrate.

### Claim 6 (depends on 1)

The semiconductor device structure of claim 1, wherein the fuse medium is embedded within the semiconductor substrate.

### Claim 7 (depends on 1)

The semiconductor device structure of claim 1, wherein the first fuse element has a first width along a second direction substantially perpendicular to the first direction, and the fuse medium has a second width less than the first width along the second direction.

### Claim 8 (depends on 1)

The semiconductor device structure of claim 1, wherein the second fuse element is located at an elevation substantially the same as that of the conductive layer.

### Claim 9 (depends on 8)

The semiconductor device structure of claim 8, wherein the second fuse element and the conductive layer are continuous.

### Claim 10 (depends on 1)

The semiconductor device structure of claim 1, wherein the first fuse element is tapered toward the first surface of the semiconductor substrate.

### Claim 11 (depends on 1)

The semiconductor device structure of claim 1, wherein the first fuse element is tapered toward the second surface of the semiconductor substrate.

### Claim 12 (depends on 1)

The semiconductor device structure of claim 1, wherein the second fuse element is tapered toward the first surface of the semiconductor substrate.