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US 12,765,345 B2Granted
Integration of fully aligned via through selective deposition and resistivity reduction
AssigneeLam Research Corporation
InventorsDennis M. Hausmann, Pankaj Ghanshyam Ramnani, Kashish Sharma, Paul C. Lemaire, Arpan Pravin Mahorowala
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Abstract
Methods and apparatuses for an integration scheme for forming a fully aligned via using selective deposition of graphene on metal surfaces and selective deposition of an inhibitor layer on exposed barrier surfaces prior to depositing dielectric material are provided.
Claims10
A method for processing substrates, the method comprising:
- providing a semiconductor substrate, wherein the semiconductor substrate includes a metal layer formed in a dielectric layer and a barrier layer between the metal layer and the dielectric layer, the metal layer having an exposed metal surface and the barrier layer having an exposed barrier surface;
- selectively depositing graphene on the exposed metal surface;
- after selectively depositing graphene on the exposed metal surface, selectively depositing an inhibitor layer on the exposed barrier surface;
- and
- selectively depositing a dielectric material on the dielectric layer.
2 more elements
A semiconductor device comprising:
- a first dielectric layer;
- a barrier layer lining the first dielectric layer;
- a first metal layer formed in the first dielectric layer on the barrier layer;
- a selective graphene film selectively formed on a top surface of the first metal layer relative to the first dielectric layer;
- a selective inhibitor layer selectively formed on a top surface of the barrier layer relative to the selective graphene film and the first dielectric layer;
- and
- a selective dielectric layer selectively formed on a top surface of the first dielectric layer relative to the first metal layer and the barrier layer.
4 more elements
An apparatus for processing substrates, the apparatus comprising:
- one or more process chambers, each process chamber comprising a chuck;
- one or more gas inlets into the process chambers and associated flow-control hardware;
- and
- a controller having at least one processor and a memory, wherein
- the at least one processor and the memory are communicatively connected with one another,
- the at least one processor is at least operatively connected with the flow-control hardware, and
- the memory stores computer-executable instructions for controlling the at least one processor to at least control the flow-control hardware to:
- cause introduction of a hydrocarbon precursor to selectively deposit graphene on an exposed metal surface of a substrate;
- cause introduction of an organometallic deposition precursor to selectively deposit an inhibitor layer on an exposed barrier surface of the substrate;
- and
- cause introduction of a dielectric deposition precursor to selectively form a dielectric material on a dielectric layer on the substrate.
8 more elements
Dependencies are inferred from the claim text.