# US 12,765,341 B2 · Semiconductor device with a liner layer and method for fabricating the same

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- Number: US 12,765,341 B2
- Document ID: US12765341B2
- Status: Granted
- Kind: B2
- Application number: 18/368,139
- Filed: 2023-09-14
- Published: 2024-06-20
- Granted: 2026-10-13
- Earliest claimed: 2022-12-08
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Tse-Yao Huang
- Web page: https://patentgrep.com/patent/US12765341B2

## CPC

- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/076: {in via holes or trenches}
- H10W 20/42: Vias, e.g. via plugs
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first dielectric layer positioned on the substrate; a first opening positioned along the first dielectric layer to expose the substrate; a first liner layer conformally positioned in the first opening and on a top surface of the first dielectric layer; an energy-removable layer positioned in the first opening; a second dielectric layer positioned on the first liner layer; and a second opening positioned along the second dielectric layer to expose the energy-removable layer. The second dielectric layer has etching selectivity to the first liner layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first dielectric layer positioned on the substrate;
a second dielectric layer positioned on the first dielectric layer;
a bottom portion positioned along the first dielectric layer and on the substrate;
a top portion positioned along the second dielectric layer and on the bottom portion; and
a first liner layer positioned between the bottom portion and the first dielectric layer, between the bottom portion and the substrate, and between the second dielectric layer and the first dielectric layer;
wherein the bottom portion and the top portion configure a conductive structure;
wherein the second dielectric layer has etching selectivity to the first liner layer;
wherein the first liner layer comprises titanium nitride, tantalum nitride, or a combination thereof;
wherein the first dielectric layer and the second dielectric layer comprise a same material.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a width of the bottom portion is less than a width of the top portion.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer comprises silicon oxide.

### Claim 4

A semiconductor device, comprising:
a substrate;
a first dielectric layer positioned on the substrate;
a second dielectric layer positioned on the first dielectric layer;
a bottom portion positioned along the first dielectric layer and on the substrate;
a top portion positioned along the second dielectric layer and on the bottom portion;
an intervening layer positioned between the first dielectric layer and the second dielectric layer; and
a first liner layer;
wherein the bottom portion and the top portion configure a conductive structure;
wherein the second dielectric layer has etching selectivity to the first liner layer;
wherein the intervening layer comprises silicon nitride, silicon oxynitride, silicon nitride oxide, or a combination thereof;
wherein the first and the second dielectric layer comprise a same material.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a width of the bottom portion is less than a width of the top portion.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the first dielectric layer comprises silicon oxide.