# US 12,765,329 B2 · Semiconductor chip, semiconductor device including semiconductor chips, and method of inspecting the semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,329 B2 - Document ID: US12765329B2 - Status: Granted - Kind: B2 - Application number: 18/635,180 - Filed: 2024-04-15 - Published: 2025-01-16 - Granted: 2026-10-13 - Earliest claimed: 2023-07-12 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Junghyun Roh; Honggyun Kim; Manhee Han; Jaeyoung Hong - Web page: https://patentgrep.com/patent/US12765329B2 ## CPC - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. The semiconductor substrate includes a circuit pattern region and a peripheral region surrounding the circuit pattern region, an activation layer on the second surface of the semiconductor substrate and having a plurality of circuit patterns in the circuit pattern region, and at least one scattering detection pattern in the peripheral region and having a plurality of circuit cells that generate leakage current based on a scattered beam or heat of a laser. ## Claims ### Claim 1 A semiconductor chip, comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface, the semiconductor substrate including a circuit pattern region and a peripheral region surrounding the circuit pattern region; an activation layer on the second surface of the semiconductor substrate, the activation layer having a plurality of circuit patterns in the circuit pattern region; and at least one scattering detection pattern in the peripheral region, the at least one scattering detection pattern having a plurality of circuit cells configured to generate a leakage current based on a scattered beam or heat of a laser. ### Claim 2 (depends on 1) The semiconductor chip of claim 1, wherein a width of the peripheral region is within a range of 30 μm to 40 μm from an outer side surface of the semiconductor substrate. ### Claim 3 (depends on 1) The semiconductor chip of claim 1, wherein the peripheral region includes a scribe lane region through which the laser moves during a semiconductor manufacturing process. ### Claim 4 (depends on 1) The semiconductor chip of claim 1, wherein the at least one scattering detection pattern is adjacent to an outer side surface of the semiconductor substrate. ### Claim 5 (depends on 1) The semiconductor chip of claim 1, wherein the peripheral region includes chamfered regions, and the at least one scattering detection pattern is in at least one of the chamfered regions. ### Claim 6 (depends on 1) The semiconductor chip of claim 1, wherein the plurality of circuit patterns include decoupling capacitors, the semiconductor chip further comprising: at least one second scattering detection pattern adjacent to a decoupling capacitor from among the decoupling capacitors in the circuit pattern region, the at least one second scattering detection pattern having a plurality of second circuit cells configured to generate a second leakage current based on the scattered beam or the heat. ### Claim 7 (depends on 1) The semiconductor chip of claim 1, wherein the plurality of circuit cells include a plurality of transistors and a plurality of capacitors. ### Claim 8 (depends on 7) The semiconductor chip of claim 7, wherein when the plurality of transistors are independently turned on while the plurality of capacitors are charged, the plurality of circuit cells are configured to generate a first potential difference, and a circuit cell from among the plurality of circuit cells that generates the leakage current based on the scattered beam or the heat of the laser is configured to generate a second potential difference different from the first potential difference. ### Claim 9 (depends on 1) The semiconductor chip of claim 1, wherein the plurality of circuit cells are arranged in a grid shape. ### Claim 10 (depends on 1) The semiconductor chip of claim 1, wherein the laser comprises a stealth laser or a conventional laser. ### Claim 11 A semiconductor device, comprising: a silicon substrate having a first surface and a second surface opposite to the first surface, the silicon substrate including a plurality of circuit pattern regions and a peripheral region between the plurality of circuit pattern regions; an activation layer on the second surface of the silicon substrate, the activation layer having a plurality of circuit patterns respectively in the plurality of circuit pattern regions; and a plurality of scattering detection patterns in the peripheral region, each of the plurality of scattering detection patterns having a plurality of circuit cells configured to generate a leakage current based on a scattered beam or heat of a laser. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the peripheral region includes a scribe lane region through which the laser moves during a semiconductor manufacturing process. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the plurality of scattering detection patterns are adjacent to a laser pass region within the scribe lane region. ### Claim 14 (depends on 11) The semiconductor device of claim 11, wherein the peripheral region includes a plurality of chamfer regions adjacent to corners of each of the plurality of circuit pattern regions, and the plurality of scattering detection patterns are in the plurality of chamfer regions. ### Claim 15 (depends on 11) The semiconductor device of claim 11, further comprising: at least one second scattering detection pattern in the plurality of circuit pattern regions, the at least one second scattering detection pattern having a plurality of second circuit cells that generate a second leakage current based on the scattered beam or the heat of the laser. ### Claim 16 (depends on 11) The semiconductor device of claim 11, wherein the plurality of circuit cells include a plurality of transistors and a plurality of capacitors. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein when the plurality of transistors are independently turned on while the plurality of capacitors are charged, the plurality of circuit cells are configured to generate a first potential difference, and a circuit cell from among the plurality of circuit cells that generates the leakage current based on the scattered beam or the heat of the laser is configured to generate a second potential difference different from the first potential difference. ### Claim 18 (depends on 11) The semiconductor device of claim 11, wherein the plurality of circuit cells are arranged in a grid shape. ### Claim 19 (depends on 11) The semiconductor device of claim 11, wherein the laser comprises a stealth laser or a conventional laser. ### Claim 20 A semiconductor chip, comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface, the semiconductor substrate including a circuit pattern region and a peripheral region surrounding the circuit pattern region; an activation layer on the second surface of the semiconductor substrate, the activation layer having a plurality of circuit patterns in the circuit pattern region; and at least one scattering detection pattern in the peripheral region, the at least one scattering detection pattern having a plurality of circuit cells configured to generate leakage current based on a scattered beam or heat of a laser, wherein the plurality of circuit cells are arranged in a grid shape, and wherein each circuit cell of the plurality of circuit cells includes a transistor and a capacitor.