# US 12,765,321 B2 · Carrier substrate for SOI structure and associated manufacturing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,321 B2 - Document ID: US12765321B2 - Status: Granted - Kind: B2 - Application number: 18/004,156 - Filed: 2021-03-30 - Published: 2023-10-05 - Granted: 2026-10-13 - Earliest claimed: 2020-07-03 - Assignees: Soitec - Applicants: Soitec - Inventors: Isabelle Bertrand; Frédéric Allibert; Romain Bouveyron; Walter Schwarzenbach - Web page: https://patentgrep.com/patent/US12765321B2 ## CPC - H10P 72/74: {using temporarily an auxiliary support} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10P 95/90: Thermal treatments, e.g. annealing or sintering - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A carrier substrate comprises monocrystalline silicon, and has a front face and a back face. The carrier substrate comprises: a surface region extending from the front face to a depth of between 800 nm and 2 microns, having less than 10 crystal-originated particles (COPs) (as detected by inspecting the surface using dark-field reflection microscopy); an upper region extending from the front face to a depth of between a few microns and 40 microns and having an interstitial oxygen (Oi) content less than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm, and a lower region extending between the upper region and the back face and having a micro-defect (BMD) concentration greater than or equal to 1E8/cm3. A method is used to manufacture such a carrier substrate. ## Claims ### Claim 1 A carrier substrate comprising monocrystalline silicon and having a front face and a back face, and the carrier substrate further comprising: a surface region extending from the front face to a depth of between 800 nm and 2 microns, the surface region having fewer than ten crystal-originated particles (COPs); an upper region extending from the front face to a depth of between a few microns and 40 microns, the upper region having an interstitial oxygen content lower than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm; and a lower region extending between the upper region and the back face, the lower region having a micro-defect concentration higher than or equal to 1E8/cm3. ### Claim 2 (depends on 1) The carrier substrate of claim 1, wherein the resistivity of the upper region is higher than or equal to 750 ohm·cm. ### Claim 3 (depends on 1) The carrier substrate of claim 1, wherein the upper region extends to a depth of between 10 microns and 30 microns. ### Claim 4 (depends on 1) The carrier substrate of claim 1, wherein the micro-defect concentration in the lower region is between 1E8/cm3 and 3E10/cm3. ### Claim 5 A silicon-on-insulator (SOI) structure, comprising: a working layer disposed on a dielectric layer, the dielectric layer disposed on a carrier substrate, the carrier substrate comprising monocrystalline silicon and having a front face and a back face, the carrier substrate further comprising: a surface region extending from the front face to a depth of between 800 nm and 2 microns, the surface region having fewer than ten crystal-originated particles (COPs); an upper region extending from the front face to a depth of between a few microns and 40 microns, the upper region having an interstitial oxygen content lower than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm; and a lower region extending between the upper region and the back face, the lower region having a micro-defect concentration higher than or equal to 1E8/cm3. ### Claim 6 (depends on 5) The SOI structure of claim 5, wherein the working layer has a thickness of less than 50 nm. ### Claim 7 (depends on 5) The SOI structure of claim 5, wherein the dielectric layer has a thickness of between 10 nm and 150 nm. ### Claim 8 An electronic component for radiofrequency or low-power logic application, comprising: a silicon-on-insulator (SOI) structure including a working layer disposed on a dielectric layer, the dielectric layer disposed on a carrier substrate, the carrier substrate comprising monocrystalline silicon and having a front face and a back face, the carrier substrate further comprising: a surface region extending from the front face to a depth of between 800 nm and 2 microns, the surface region having fewer than ten crystal-originated particles (COPs); an upper region extending from the front face to a depth of between a few microns and 40 microns, the upper region having an interstitial oxygen content lower than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm; and a lower region extending between the upper region and the back face, the lower region having a micro-defect concentration higher than or equal to 1E8/cm3; and at least one transistor disposed on and/or in the working layer of the SOI structure. ### Claim 9 A method for manufacturing a carrier substrate, the method comprising: a) providing a substrate comprising monocrystalline silicon, the substrate having an interstitial oxygen content between 12E17 Oi/cm3 and 16E17 Oi/cm3 and a resistivity higher than 500 ohm·cm; b) applying a first heat treatment at a temperature between 1150° C. and 1250° C., under a neutral or reducing atmosphere, for a duration longer than or equal to 30 min, to form a surface region and an upper region in the substrate, the surface region extending from a front face of the substrate to a depth of between 800 nm and 2 microns, the surface region having fewer than ten crystal-originated particles (COPs), the upper region extending from the front face to a depth of between a few microns and 40 microns, the upper region having an interstitial oxygen content lower than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm; and c) applying a second heat treatment comprising a first sequence of annealing at a temperature between 600° C. and 900° C., and a second sequence of annealing at a temperature between 950° C. and 1100° C., to form a lower region in the substrate, the lower region extending between the upper region and a back face of the substrate, the lower region having a micro-defect concentration higher than or equal to 1E8/cm3. ### Claim 10 (depends on 9) The method of claim 9, wherein the first sequence of the second heat treatment comprises two temperature plateaus including a first plateau between 650° C. and 700° C., and a second plateau around 800° C. ### Claim 11 (depends on 2) The carrier substrate of claim 2, wherein the resistivity of the upper region is higher than or equal to 1000 ohm·cm. ### Claim 12 (depends on 4) The carrier substrate of claim 4, wherein the micro-defect concentration in the lower region is between 1E9/cm3 and 2E10/cm3. ### Claim 13 (depends on 6) The SOI structure of claim 6, wherein the working layer has a thickness of between 4 nm and 25 nm.