# US 12,765,300 B2 · Wafer dicing method forming internal cracks by laser beam and method of manufacturing semiconductor device by using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,300 B2 - Document ID: US12765300B2 - Status: Granted - Kind: B2 - Application number: 18/519,501 - Filed: 2023-11-27 - Published: 2024-05-30 - Granted: 2026-10-13 - Earliest claimed: 2022-11-28 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jesung Kim; Haemin Park; Heejae Nam; Junggeun Shin; Junho Yoon; Jungho Choi - Web page: https://patentgrep.com/patent/US12765300B2 ## CPC - H10P 54/30: by forming weakened zones for subsequent cutting or separating, e.g. by laser treatment or by ion implantation - B23K 26/53: for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks - H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 58/20: {comprising two or more processes, e.g. etching and cutting} - H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes} - B23K 2101/40: Semiconductor devices - H10P 72/7416: {used during dicing or grinding} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM ## Abstract A wafer dicing method includes preparing a wafer having a plurality of device formation areas and a scribe lane area defining the plurality of device formation areas, forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer, forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction, forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves, forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves, and separating the plurality of semiconductor devices from each other along the one or more internal cracks. ## Claims ### Claim 1 A wafer dicing method, comprising: preparing a wafer having a plurality of device formation areas and a scribe lane area between the plurality of device formation areas; forming a plurality of semiconductor devices in the respective plurality of device formation areas of the wafer; forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction; forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves; forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves; and separating the plurality of semiconductor devices from each other along the one or more internal cracks. ### Claim 2 (depends on 1) The wafer dicing method of claim 1, wherein the planarizing of the lower surfaces of the plurality of first grooves comprises configuring the lower surface of each of the plurality of first grooves to have a roughness of less than or equal to about 0.08 micrometers. ### Claim 3 (depends on 1) The wafer dicing method of claim 1, wherein the forming of the plurality of first grooves in the scribe lane area comprises performing a laser etching method or a plasma etching method. ### Claim 4 (depends on 1) The wafer dicing method of claim 1, wherein the planarizing of the lower surfaces of the plurality of first grooves comprises performing a laser etching method or a chemical mechanical polish (CMP) method. ### Claim 5 (depends on 1) The wafer dicing method of claim 1, wherein a first laser beam for planarizing the lower surfaces of the plurality of first grooves has a different wavelength and irradiation area relative to a second laser beam for forming the one or more internal cracks. ### Claim 6 (depends on 1) The wafer dicing method of claim 1, wherein the planarizing of the lower surfaces of the plurality of first grooves comprises removing at least a portion of the wafer in a vertical direction by greater than or equal to about 1 micrometer. ### Claim 7 (depends on 1) The wafer dicing method of claim 1, wherein a range of a width of each of the plurality of second grooves in a horizontal direction is from about 10 micrometers to about 100 micrometers. ### Claim 8 A method of manufacturing a semiconductor device, the method comprising: preparing a wafer having a plurality of device formation areas and a scribe lane area between the plurality of device formation areas; forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer; forming a plurality of insulating layers and a wiring layer on the wafer; forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction; forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves; forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves; separating the plurality of semiconductor devices from each other along the one or more internal cracks; and packaging each of the plurality of semiconductor devices responsive to the separating, wherein the plurality of first grooves pass through at least one of the plurality of insulating layers and the wiring layer in the vertical direction. ### Claim 9 (depends on 8) The method of claim 8, wherein the planarizing of the lower surfaces of the plurality of first grooves comprises performing planarizing by at least a portion of a polishing apparatus having a rotation shaft in the vertical direction rotating inside the plurality of first grooves. ### Claim 10 (depends on 8) The method of claim 8, wherein the plurality of second grooves and the one or more internal cracks respectively overlap each other in the vertical direction. ### Claim 11 (depends on 8) The method of claim 8, wherein the lower surfaces of the plurality of second grooves and the one or more internal cracks are spaced apart from each other in the vertical direction. ### Claim 12 (depends on 8) The method of claim 8, wherein the separating of the plurality of semiconductor devices comprises: attaching a dicing tape onto a back surface of the wafer; and stretching the dicing tape in a horizontal direction. ### Claim 13 (depends on 8) The method of claim 8, wherein strengths of the plurality of insulating layers are less than a strength of the wafer. ### Claim 14 (depends on 8) The method of claim 8, further comprising grinding a back surface of the wafer before the forming of the one or more internal cracks in the wafer. ### Claim 15 (depends on 8) The method of claim 8, further comprising grinding a back surface of the wafer after the forming of the one or more internal cracks in the wafer. ### Claim 16 A method of manufacturing a semiconductor device, the method comprising: preparing a plurality of device formation areas and a scribe lane area between the plurality of device formation areas on a wafer; forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer; forming a plurality of insulating layers and a wiring layer on the wafer; forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction; forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves; forming one or more internal cracks in the wafer by irradiating the scribe lane area with a laser beam along lower surfaces of the plurality of second grooves; separating the plurality of semiconductor devices from each other along the one or more internal cracks; and packaging each of the plurality of semiconductor devices responsive to the separating, wherein the forming of the plurality of first grooves in the scribe lane area comprises performing at least one of a laser etching method using a first laser device, and a plasma etching method, the planarizing of the lower surfaces of the plurality of first grooves comprises performing at least one of a laser etching method using a second laser device, and a chemical mechanical polish (CMP) method, the forming of the one or more internal cracks comprises performing a laser etching method using a third laser device, and the plurality of first grooves pass through at least one of the plurality of insulating layers and the wiring layer in the vertical direction. ### Claim 17 (depends on 16) The method of claim 16, wherein the forming of the plurality of first and second grooves comprises using the first and second laser devices, respectively, to etch at least a portion of each of the plurality of insulating layers or the wafer, and the forming of the one or more internal cracks comprises using the third laser device to reform at least a portion of the wafer by irradiating a laser beam to an area inside of the wafer. ### Claim 18 (depends on 16) The method of claim 16, wherein an irradiation range of a laser beam generated by the second laser device is wider than an irradiation range of the laser beam generated by the third laser device. ### Claim 19 (depends on 16) The method of claim 16, wherein a wavelength of a laser beam generated by the second laser device is shorter than a wavelength of a laser beam generated by the third laser device. ### Claim 20 (depends on 16) The method of claim 16, wherein forming the plurality of second grooves comprises forming the lower surface of each of the plurality of second grooves to have a surface roughness of less than or equal to about 0.08 micrometers, and a range of a horizontal width of each of the plurality of second grooves from about 60 micrometers to about 100 micrometers.