# US 12,765,284 B2 · Silicon carbide semiconductor device and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,284 B2 - Document ID: US12765284B2 - Status: Granted - Kind: B2 - Application number: 18/493,272 - Filed: 2023-10-24 - Published: 2024-02-15 - Granted: 2026-10-13 - Earliest claimed: 2021-11-30 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Yoshihito Ichikawa; Akimasa Kinoshita - Web page: https://patentgrep.com/patent/US12765284B2 ## CPC - H10P 32/18: {Diffusion lifetime killers} - H10D 12/031: {of IGBTs} - H10D 30/665: {having edge termination structures} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/109: {Reduced surface field [RESURF] PN junction structures} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 62/53: the imperfections being within the semiconductor body - H10D 62/8325: {Silicon carbide} - H10P 30/22: using masks - H10P 32/171: {being group IV material} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A manufacturing method of a silicon carbide semiconductor device includes: epitaxially growing a drift layer of a first conductivity-type on a silicon carbide substrate of the first conductivity-type; forming a base region of a second conductivity-type on the drift layer; forming a main region of the first conductivity-type on the drift layer so as to be in contact with the base region; forming a gate insulating film so as to be in contact with the base region and the main region; forming a gate electrode so as to be in contact with the base region and the main region with the gate insulating film interposed; and forming a lifetime killer region at a depth covering a bottom surface of the drift layer by irradiating the top surface side of the drift layer with a lifetime killer after epitaxially growing the drift layer and before forming the gate insulating film. ## Claims ### Claim 1 A silicon carbide semiconductor device comprising: a drift layer of a first conductivity-type provided on a top surface side of a silicon carbide substrate of the first conductivity-type; a base region of a second conductivity-type provided on a top surface side of the drift layer; a main region of the first conductivity-type provided on the top surface side of the drift layer so as to be in contact with the base region; an insulated gate electrode structure provided to be in contact with the main region and the base region; a buffer layer of the first conductivity-type provided between the silicon carbide substrate and the drift layer; and a lifetime killer region provided to cover a bottom surface of the drift layer and including a recombination center having a point defect, wherein a concentration peak of a concentration profile of the point defect in a depth direction is located: inside the drift layer, inside the buffer layer, or inside the silicon carbide substrate. ### Claim 2 (depends on 1) The silicon carbide semiconductor device of claim 1, wherein the concentration peak is located inside the silicon carbide substrate under an interface between the silicon carbide substrate and the drift layer. ### Claim 3 (depends on 1) The silicon carbide semiconductor device of claim 1, wherein: a mesa groove is provided in an edge termination region provided at a circumference of an active region provided with the insulated gate electrode structure; and the lifetime killer region is flat from the active region to the edge termination region. ### Claim 4 (depends on 1) The silicon carbide semiconductor device of claim 1, wherein: a mesa groove is provided in an edge termination region provided at a circumference of an active region provided with the insulated gate electrode structure; and the lifetime killer region in the edge termination region is provided at a deeper position than the lifetime killer region in the active region. ### Claim 5 (depends on 1) The silicon carbide semiconductor device of claim 1, wherein the concentration peak is located in a range of: shallower than an interface between the buffer layer and the drift layer by a first distance, the first distance corresponding to a full width at half maximum (FWHM) of the concentration peak, and deeper than the interface by a second distance, the second distance corresponding to five times the FWHM, wherein the range is inclusive of end points. ### Claim 6 (depends on 1) The silicon carbide semiconductor device of claim 1, wherein the concentration peak is located between an interface between the buffer layer and the drift layer and a distance shallower than the interface by a distance corresponding to a full width at half maximum of the concentration peak. ### Claim 7 (depends on 1) The silicon carbide semiconductor device of claim 1, wherein the concentration peak is located between an interface between the buffer layer and the drift layer and a distance deeper than the interface by a distance corresponding to five times a full width at half maximum of the concentration peak. ### Claim 8 A silicon carbide semiconductor device comprising: a drift layer of a first conductivity-type provided on a top surface side of a silicon carbide substrate of the first conductivity-type; a base region of a second conductivity-type provided on a top surface side of the drift layer; a main region of the first conductivity-type provided on the top surface side of the drift layer so as to be in contact with the base region; an insulated gate electrode structure provided to be in contact with the main region and the base region; a lifetime killer region provided to cover a bottom surface of the drift layer and including a recombination center having a point defect; and a buffer layer of the first conductivity-type provided between the silicon carbide substrate and the drift layer and having a higher impurity concentration than the drift layer, wherein a peak position of a concentration of the point defect in a depth direction is located inside the buffer layer. ### Claim 9 A method of manufacturing a silicon carbide semiconductor device, comprising: epitaxially growing a drift layer of a first conductivity-type on a top surface side of a silicon carbide substrate of the first conductivity-type; forming a base region of a second conductivity-type on a top surface side of the drift layer; forming a main region of the first conductivity-type on the top surface side of the drift layer so as to be in contact with the base region; forming a gate insulating film so as to be in contact with the base region and the main region; forming a gate electrode so as to be in contact with the base region and the main region with the gate insulating film interposed: and forming a lifetime killer region at a depth covering a bottom surface of the drift layer by irradiating the top surface side of the drift layer with a lifetime killer after the epitaxially growing the drift layer and before the forming the gate insulating film. ### Claim 10 (depends on 9) The method of manufacturing the silicon carbide semiconductor device of claim 9, wherein the lifetime killer is protons or helium ions. ### Claim 11 (depends on 9) The method of manufacturing the silicon carbide semiconductor device of claim 9, further comprising forming a trench penetrating the base region and the main region, wherein the forming the lifetime killer region is executed before the forming the trench. ### Claim 12 (depends on 9) The method of manufacturing the silicon carbide semiconductor device of claim 9, further comprising executing activation annealing for activating impurity ions implanted into the base region and the main region, wherein the forming the lifetime killer region is executed before the executing the activation annealing. ### Claim 13 (depends on 9) The method of manufacturing the silicon carbide semiconductor device of claim 9, wherein the forming the lifetime killer region is executed immediately after the epitaxially growing the drift layer. ### Claim 14 (depends on 9) The method of manufacturing the silicon carbide semiconductor device of claim 9, further comprising forming a mesa groove in an edge termination region provided at a circumference of an active region provided with the gate electrode, wherein the forming the lifetime killer region is executed before the forming the mesa groove. ### Claim 15 (depends on 9) The method of manufacturing the silicon carbide semiconductor device of claim 9, further comprising forming a mesa groove in an edge termination region provided at a circumference of an active region provided with the gate insulating film and the gate electrode, wherein the forming the lifetime killer region is executed after the forming the mesa groove. ### Claim 16 (depends on 9) The method of manufacturing the silicon carbide semiconductor device of claim 9, further comprising forming a buffer layer of the first conductivity-type having a higher impurity concentration than the drift layer on the silicon carbide substrate before the epitaxially growing the drift layer. ### Claim 17 (depends on 10) The method of manufacturing the silicon carbide semiconductor device of claim 10, wherein a dose of the protons or helium ions is 1×1010 cm−2 or greater and 2×1012 cm−2 or smaller.