Memory device, memory array, and memory unit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
Life of this patent
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Abstract
The disclosure provides a memory device, a memory array, and an N-bit memory unit. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.
Claims20
A memory device, comprising:
- a memory array, comprising a memory unit forming one word in the memory array, wherein the memory unit comprises a least significant bit (LSB) part and a most significant bit (MSB) part;
- wherein the LSB part comprises:
- a first memory cell, configured to store at least two bits of LSBs of the word, wherein the first memory cell is a phase change memory cell including GST with a specific percentage of Nitrogen doping,
- and wherein the MSB part comprises:
- at least one second memory cell, configured to store only one bit of MSB of the word.
A memory array, comprising:
- a memory unit forming one word in the memory array, wherein the memory unit comprises a least significant bit (LSB) part and a most significant bit (MSB) part;
- wherein the LSB part comprises:
- a first memory cell, configured to store at least two bits of at least two first bits of LSBs of the word;
- a second memory cell, configured to store at least two bits of at least two second bits of the LSBs, wherein the first memory cell is a phase change memory cell including Ge2Sb2Te5 with a first percentage of Nitrogen doping;
- and
- wherein the MSB part comprises:
- at least one third memory cell, configured to store only one bit of MSB of the word, wherein the third memory cell is a phase change memory cell including Ge2Sb2Te5 with a second percentage of Nitrogen doping.
A memory unit, wherein the memory unit forms one word in a memory array, the memory unit comprises a least significant bit (LSB) part and a most significant bit (MSB) part;
- wherein the LSB part comprises:
- a first memory cell, configured to store at least two bits of LSBs of the word, and the first memory cell is a resistive random access memory (RRAM) cell,
- and wherein the MSB part comprises:
- at least one second memory cell, configured to store only one bit of MSB of the word.
Dependencies are inferred from the claim text.