Manufacturing method of memory device with removal of top electrode
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHarry-Hak-Lay Chuang, Hung-Cho Wang, Sheng-Chang Chen, Jun-Yao Chen, Chang-Jen Hsieh
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Abstract
A method for manufacturing a memory device includes forming a dielectric layer over a substrate, in which the substrate has a cell region and a logic region adjacent to the cell region. A bottom electrode, a memory layer, and a top electrode are formed in sequence over the cell region of the substrate. A first spacer is formed extending upwards from the bottom electrode. A second spacer is formed extending upwards from the dielectric layer and lining with sidewalls of the bottom electrode and the first spacer.
Claims16
A method, comprising:
- forming a dielectric layer over a substrate, wherein the substrate has a cell region and a logic region adjacent to the cell region;
- forming a bottom electrode, a memory layer, and a top electrode in sequence over the cell region of the substrate;
- forming a first spacer extending upwards from the bottom electrode;
- depositing a dielectric material over the dielectric layer on the cell region and the logic region;
- etching the dielectric material to form a second spacer extending upwards from the dielectric layer and lining with sidewalls of the bottom electrode and the first spacer and to remove the dielectric material entirely from the logic region, wherein the second spacer is made of the dielectric material and has a bottom surface lower than a top surface of the bottom electrode;
- etching the top electrode to expose a top surface of the memory layer and an inner sidewall of the first spacer, wherein after etching the top electrode, the exposed top surface of the memory layer is lower than the exposed inner sidewall of the first spacer;
- and
- after etching the top electrode, forming a top electrode via on the memory layer.
A method, comprising:
- forming a conductive feature embedded in a first dielectric layer;
- forming a bottom electrode on the conductive feature, wherein the bottom electrode is electrically connected to the conductive feature;
- forming a magnetic tunnel junction (MTJ) layer over the bottom electrode;
- forming a top electrode over the MTJ layer;
- forming a first spacer over the bottom electrode, wherein the first spacer lines with a sidewall of the MTJ layer;
- forming a top electrode via over the MTJ layer, wherein the top electrode via is in direct contact with the MTJ layer, wherein forming the top electrode via over the MTJ layer comprises:
- etching the top electrode such that a recess is formed on the MTJ layer;
- and
- after etching the top electrode, depositing a second dielectric layer covering the MTJ layer and the first spacer, wherein the second dielectric layer is disposed in the recess;
- and
- forming an etch stop layer overlapping a top surface of the first spacer and in direct contact with an inner sidewall of the first spacer.
Dependencies are inferred from the claim text.