Semiconductor structure including stress tuning structure and method for forming the same

A semiconductor structure, comprising:

• a substrate, having a first surface and a second surface opposite to the first surface;
• a cavity, disposed on the second surface of the substrate, wherein a portion of the substrate at a bottom of the cavity defines a diaphragm portion and a cantilever portion surrounding the diaphragm portion, and a portion of the substrate surrounding the cavity defines an anchor portion;
• a piezoelectric capacitor, disposed over the first surface of the substrate and surrounding the diaphragm portion;
• a first dielectric layer, disposed over the piezoelectric capacitor;
• and
• a second dielectric layer, disposed over the first dielectric layer, wherein a portion of the first dielectric layer proximal to the diaphragm portion is exposed through the second dielectric layer from a top-view perspective.

A method of manufacturing a semiconductor structure, comprising:

• forming a plurality of piezoelectric capacitors over a first surface of a substrate;
• forming a first dielectric layer over the substrate or the plurality of piezoelectric capacitors;
• changing a stress of the first dielectric layer in one of a central region and a peripheral region of the substrate while a stress of the first dielectric layer in the other one of the central region and the peripheral region remaining the same, wherein the central region is surrounded by the peripheral region;
• forming a plurality of cavities on a second surface of the substrate opposite to the first surface;
• and
• dicing the substrate into a plurality of chips.