Display substrate, preparation method therefor, and display apparatus

A display substrate, comprising a drive circuit layer arranged on a base substrate and a light emitting structure layer arranged at a side of the drive circuit layer away from the base substrate, wherein:

• the drive circuit layer comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and the light emitting structure layer comprises a plurality of light emitting units forming a plurality of pixel rows and a plurality of pixel columns;
• at least one circuit unit comprises at least a pixel drive circuit, a light emitting unit comprises at least one anode, and the at least one anode of the at least one light emitting unit is connected to the pixel drive circuit of a corresponding circuit unit;
• at least one circuit unit is provided with at least one light transmitting region located between adjacent anodes;
• there is a first dimension between two adjacent anodes in two adjacent pixel rows, and the light transmitting region has a second dimension, a ratio of the second dimension to the first dimension is greater than or equal to 0.5, the first dimension is a minimum distance between edges of two adjacent anodes, and the second dimension is a maximum distance between edges of the light transmitting region;
• the pixel drive circuit at least comprises a storage capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor;
• in the circuit unit of at least one circuit row, a first electrode of the first transistor is connected to an initial signal line, a second electrode of the second transistor is connected to a second electrode of the third transistor, a first electrode of the third transistor is connected to a second electrode of the fourth transistor, and a first electrode of the fourth transistor is connected to a data signal line;
• the second transistor of at least one circuit unit of an M-th circuit row is arranged at a side of the storage capacitance close to an (M+1)-th circuit row, the first transistor of the at least one circuit unit of the M-th circuit row is arranged at a side of the storage capacitance away from the (M+1)-th circuit row, a first electrode of the second transistor of the at least one circuit unit of the M-th circuit row and a second electrode of the first transistor of the at least one circuit unit of the (M+1)-th circuit row are connected with each other to be of an integral structure, and M is a positive integer greater than or equal to 1;
• and
• at least one circuit unit further comprises a first scan signal line and a second scan signal line, the first scan signal line is connected to a gate electrode of the second transistor and a gate electrode of the fourth transistor, the second scan signal line is connected to a gate electrode of the first transistor;
• the first scan signal line of at least one circuit unit of the M-th circuit row is arranged at a side of the storage capacitance close to the (M+1)-th circuit row, and the second scan signal line of at least one circuit unit of the M-th circuit row is arranged at a side of the storage capacitance away from the (M+1)-th circuit row.