Display device having an alignment area surrounded by bank patterns

A display device comprising:

• a plurality of pixels, each of the plurality of pixels including:
• bank patterns disposed on a substrate, extended in a first direction, and spaced apart from one another in a second direction intersecting the first direction;
• a bank disposed on the bank patterns and partitioning a light emission area,
• a plurality of first electrodes disposed on the bank patterns;
• a plurality of second electrodes disposed on the bank patterns;
• a plurality of subpixels including:
• a first subpixel including a plurality of light emitting elements on a first electrode of the plurality of first electrodes and a second electrode of the plurality of second electrodes;
• a second subpixel including a plurality of light emitting elements on a first electrode of the plurality of first electrodes and a second electrode of the plurality of second electrodes, and disposed adjacent to the first subpixel in a second direction;
• and
• a third subpixel including a plurality of light emitting elements on a first electrode of the plurality of first electrodes and a second electrode of the plurality of second electrodes, and disposed adjacent to the second subpixel in the second direction;
• a first scan line extended in the first direction;
• a first gate pattern overlapping the first scan line in a plan view and electrically connected to the first scan line;
• and
• a first conductive pattern overlapping the first scan line and the first gate pattern in a plan view and electrically connected to the first scan line, wherein
• the plurality of first electrodes and the plurality of second electrodes are spaced apart from one another in the second direction,
• the first scan line, the first gate pattern, and the first conductive pattern are disposed in the first subpixel,
• the bank and the bank patterns partition an alignment area, in which the light emitting elements are disposed, in each of the plurality of subpixels, and
• an area in which the first scan line and the first gate pattern overlap one another in a plan view, is about 80% or more of an overall area of the alignment area of the first subpixel surrounded by the bank and the bank patterns, in a plan view and defined as an area between the bank patterns.

An electronic device comprising:

• a plurality of pixels, each of the plurality of pixels including:
• bank patterns disposed on a substrate, extended in a first direction, and spaced apart from one another in a second direction;
• a bank disposed on the bank patterns and partitioning a light emission area,
• a plurality of first electrodes disposed on the bank patterns;
• a plurality of second electrodes disposed on the bank patterns;
• a plurality of subpixels including:
• a first subpixel including a plurality of light emitting elements on a first electrode of the plurality of first electrodes and a second electrode of the plurality of second electrodes;
• a second subpixel including a plurality of light emitting elements on a first electrode of the plurality of first electrodes and a second electrode of the plurality of second electrodes, and disposed adjacent to the first subpixel in a second direction;
• and
• a third subpixel including a plurality of light emitting elements on a first electrode of the plurality of first electrodes and a second electrode of the plurality of second electrodes, and disposed adjacent to the second subpixel in the second direction;
• a first scan line extended in the first direction;
• a first gate pattern overlapping the first scan line in a plan view and electrically connected to the first scan line;
• and
• a first conductive pattern overlapping the first scan line and the first gate pattern in a plan view and electrically connected to the first scan line, wherein
• the plurality of first electrodes and the plurality of second electrodes are spaced apart from one another in the second direction,
• the first scan line, the first gate pattern, and the first conductive pattern are disposed in the first subpixel,
• the bank and the bank patterns partition an alignment area, in which the light emitting elements are disposed, in each of the plurality of subpixels, and
• an area in which the first scan line and the first gate pattern overlap one another in a plan view, is about 80% or more in the alignment area of the first subpixel,
• wherein the third subpixel includes:
• a first data line extended in the first direction;
• a second data line extended in the first direction;
• a third data line extended in the first direction;
• second conductive patterns electrically connected to the first data line, the second data line, and the third data line, respectively;
• and
• a second capacitance electrode extended from the second subpixel, and the first to third data lines are spaced apart from one another in the second direction.