# US 12,765,130 B2 · Radiation-emitting semiconductor chip and method for producing a radiation-emitting semiconductor chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,130 B2 - Document ID: US12765130B2 - Status: Granted - Kind: B2 - Application number: 18/260,621 - Filed: 2021-01-19 - Published: 2024-02-22 - Granted: 2026-10-13 - Earliest claimed: 2021-01-19 - Assignees: ams-OSRAM International GmbH - Applicants: ams-OSRAM International GmbH - Inventors: Fabian Kopp; Attila Molnar; Hong Pin Loh; Ban Loong Chris Ng - Web page: https://patentgrep.com/patent/US12765130B2 ## CPC - H10H 20/841: Reflective coatings, e.g. dielectric Bragg reflectors - H10W 90/00: Package configurations - H10H 20/034: {of coatings} - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A radiation-emitting semiconductor chip may include a semiconductor layer sequence having a first semiconductor layer of a first doping type and a second semiconductor layer of a second doping type. The chip may also include a first dielectric layer and a second dielectric layer arranged on the semiconductor layer sequence. A first recess may be arranged in the semiconductor layer sequence in a border region of the radiation-emitting semiconductor chip completely penetrating the first semiconductor layer. The first dielectric layer may cover the semiconductor layer sequence in the border region completely. The border region may be free of the second dielectric layer in an edge region. In addition, a method is disclosed for producing a radiation-emitting semiconductor chip. ## Claims ### Claim 1 A radiation-emitting semiconductor chip comprising: a semiconductor layer sequence comprising a first semiconductor layer of a first doping type and a second semiconductor layer of a second doping type; a first dielectric layer and a second dielectric layer arranged on the semiconductor layer sequence; wherein: a first recess is arranged in the semiconductor layer sequence in a border region of the radiation-emitting semiconductor chip completely penetrating the first semiconductor layer, the first dielectric layer covers the semiconductor layer sequence in the border region completely, and the border region is free of the second dielectric layer in an edge region, wherein the second dielectric layer comprises a plurality of sublayers on a side surface of the semiconductor layer sequence and layer thicknesses of the sublayers are tapered in the border region in direction to the edge region; and a third dielectric layer arranged between the second dielectric layer and the semiconductor layer sequence, wherein the first dielectric layer is in direct contact with a top surface of the third dielectric layer in the edge region. ### Claim 2 (depends on 1) The radiation-emitting semiconductor chip according to claim 1, wherein: the semiconductor layer sequence is configured to emit electromagnetic radiation from a radiation exit surface, and the first dielectric layer and the second dielectric layer are arranged opposite the radiation exit surface. ### Claim 3 (depends on 1) The radiation-emitting semiconductor chip according to claim 1, wherein the second dielectric layer is a distributed Bragg reflector. ### Claim 4 (depends on 1) The radiation-emitting semiconductor chip according to claim 1, wherein the first dielectric layer and the third dielectric layer have a combined thickness of at most 3 μm. ### Claim 5 (depends on 1) The radiation-emitting semiconductor chip according to claim 1, wherein the semiconductor layer sequence is arranged on a substrate. ### Claim 6 (depends on 5) The radiation-emitting semiconductor chip according to claim 5, wherein the substrate has a structured main surface. ### Claim 7 (depends on 1) The radiation-emitting semiconductor chip according to claim 1, wherein a second recess completely penetrates the second semiconductor layer, wherein a lateral extent that defines the second recess is completely within a lateral extent that defines the first recess. ### Claim 8 (depends on 1) The radiation-emitting semiconductor chip according to claim 1, wherein the side surface of the second dielectric layer is inclined with respect to a main extension plane of the radiation-emitting semiconductor chip. ### Claim 9 (depends on 1) The radiation-emitting semiconductor chip according to claim 1, wherein the second dielectric layer comprises a plurality of sublayers and layer thicknesses of the sublayers in the border region are constant in direction to the edge region. ### Claim 10 (depends on 1) The radiation-emitting semiconductor chip according to claim 1, wherein the radiation-emitting semiconductor chip is a flip chip. ### Claim 11 A method for producing a radiation-emitting semiconductor chip, wherein the method comprises: providing a semiconductor wafer comprising a first semiconductor wafer layer of a first doping type and a second semiconductor wafer layer of a second doping type; producing a first separation recess within the semiconductor wafer in a separation region completely penetrating the first semiconductor wafer layer; applying a first dielectric layer on the semiconductor wafer such that the first dielectric layer completely covers the semiconductor wafer in the separation region; applying a second dielectric layer on the semiconductor wafer such that the separation region is free of the second dielectric layer in a central region, wherein the second dielectric layer comprises a plurality of sublayers on a side surface of the semiconductor layer sequence and layer thicknesses of the sublayers are tapered in a border region in direction to an edge region; applying a third dielectric layer between the second dielectric layer and the semiconductor wafer, wherein the first dielectric layer is in direct contact with a top surface of the third dielectric layer in the edge region; and separating the semiconductor wafer through the central region into radiation emitting semiconductor chips. ### Claim 12 (depends on 11) The method according to claim 11, wherein the second dielectric layer is applied on the separation region completely, and the second dielectric layer is removed from the separation region in the central region. ### Claim 13 (depends on 12) The method according to claim 12, wherein the second dielectric layer is removed from the separation region in the central region by an etching process. ### Claim 14 (depends on 12) The method according to claim 12, wherein the second dielectric layer is removed by a lift-off process. ### Claim 15 (depends on 11) The method according to claim 11, wherein the semiconductor wafer is separated by a stealth dicing process.