LED circuit board structure, LED testing and packaging method and LED pixel package

An LED circuit board structure, comprising:

• a plurality of first color LEDs, each of the first color LEDs comprising a first P-type electrode and a first N-type electrode;
• a plurality of second color LEDs, each of the second color LEDs comprising a second P-type electrode and a second N-type electrode;
• a plurality of third color LEDs, each of the third color LEDs comprising a third P-type electrode and a third N-type electrode;
• a plurality of integrated circuit chips, each of the integrated circuit chips electrically connecting each of the first color LEDs, each of the second color LEDs and each of the third color LEDs;
• a carrier board comprising a carrying surface and a bottom surface opposite to each other, the carrying surface comprising a plurality of pixel-front-side-pattern regions disposed in intervals, the bottom surface comprising a plurality of pixel-back-side-pattern regions respectively corresponding to the pixel-front-side-pattern regions, wherein one of the first color LEDs, one of the second color LEDs, one of the third color LEDs and one of the integrated circuit chips are disposed in one of the pixel-front-side-pattern regions;
• a plurality of first P-type pads located at the carrying surface of the carrier board, wherein one of the first P-type pads is disposed at one of the pixel-front-side-pattern regions for mounting one of the first P-type electrodes;
• a plurality of second P-type pads located at the carrying surface of the carrier board, wherein one of the second P-type pads is disposed at one of the pixel-front-side-pattern regions for mounting one of the second P-type electrodes;
• a plurality of third P-type pads located at the carrying surface of the carrier board, wherein one of the third P-type pads is disposed at one of the pixel-front-side-pattern regions for mounting one of the third P-type electrodes;
• a plurality of first color pads located at the carrying surface of the carrier board, wherein one of the first color pads is disposed at one of the pixel-front-side-pattern regions for mounting a first pin of the integrated circuit chip that is disposed at the same pixel-front-side-pattern region, and for electrically connecting the first P-type pad that is disposed at the same pixel-front-side-pattern region;
• a plurality of second color pads located at the carrying surface of the carrier board, wherein one of the second color pads is disposed at one of the pixel-front-side-pattern regions for mounting a second pin of the integrated circuit chip that is disposed at the same pixel-front-side-pattern region, and for electrically connecting the second P-type pad that is disposed at the same pixel-front-side-pattern region;
• a plurality of third color pads located at the carrying surface of the carrier board, wherein one of the third color pads is disposed at one of the pixel-front-side-pattern regions for mounting a third pin of the integrated circuit chip that is disposed at the same pixel-front-side-pattern region, and for electrically connecting the third P-type pad that is disposed at the same pixel-front-side-pattern region;
• a plurality of first testing wires located at the carrying surface of the carrier board, wherein one of the first testing wires is disposed at one of the pixel-front-side-pattern regions and extends from the first color pad that is disposed at the same pixel-front-side-pattern region;
• a plurality of first connecting wires, each of the first connecting wires electrically connecting two of the first testing wires of adjacent two of the pixel-front-side-pattern regions in parallel;
• a plurality of first data wires, each of the first data wires extending along a first direction;
• a plurality of second testing wires located at the bottom surface of the carrier board, wherein one of the second testing wires is disposed at one of the pixel-back-side-pattern regions and electrically connects the second color pads that is disposed at the pixel-front-side-pattern region where the one of the pixel-back-side-pattern corresponds;
• a plurality of second connecting wires, each of the second connecting wires electrically connecting two of the second testing wires of adjacent two of the pixel-back-side-pattern regions in parallel;
• a plurality of second data wires, each of the second data wires extending along a second direction;
• a plurality of third testing wires located at the bottom surface of the carrier board, wherein one of the third testing wires is disposed at one of the pixel-back-side-pattern regions and electrically connects the third color pads that is disposed at the pixel-front-side-pattern region where the one of the pixel-back-side-pattern corresponds;
• a plurality of third connecting wires, each of the third connecting wires electrically connecting two of the third testing wires of adjacent two of the pixel-back-side-pattern regions in parallel;
• and
• a plurality of third data wires, each of the third data wires extending along the second direction;
• wherein the first color LEDs are arranged in a plurality of rows parallel to the first direction, each of the first data wires is signally connected to the first connecting wires of each of the rows, and each of the first data wires is powered to test the first color LEDs of each of the rows;
• wherein the second color LEDs are arranged in a plurality of columns parallel to the second direction, each of the second data wires is signally connected to the second connecting wires of each of the columns, and each of the second data wires is powered to test the second color LEDs of each of the columns;
• wherein the third color LEDs are arranged in the rows, each of the third data wires is signally connected to the third connecting wires of each of the rows, and each of the third data wires is powered to test the third color LEDs of each of the rows.