# US 12,765,104 B2 · Semiconductor device with resistor and method for manufacturing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,104 B2 - Document ID: US12765104B2 - Status: Granted - Kind: B2 - Application number: 18/001,767 - Filed: 2021-04-06 - Published: 2023-08-31 - Granted: 2026-10-13 - Earliest claimed: 2020-06-29 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: Hirokazu Ejiri; Jun Ogi; Yuki Kawahara; Chigusa Yamane - Web page: https://patentgrep.com/patent/US12765104B2 ## CPC - H10F 39/811: {Interconnections} - H10D 1/47: Resistors having no potential barriers - H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides} - H10F 30/225: the potential barrier working in avalanche mode, e.g. avalanche photodiodes - H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12} - H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers} - H10F 39/8063: {Microlenses} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract To provide a semiconductor device with which it is possible to reduce parasitic capacitance between electrodes for a resistance element, and a method for manufacturing the semiconductor device. A semiconductor device according to the present disclosure includes: a substrate; a first resistance layer provided on the substrate; a first electrode in contact with a lower surface of the first resistance layer; and a second electrode in contact with an upper surface of the first resistance layer. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; a first resistance layer provided on the substrate; a first electrode in contact with a lower surface of the first resistance layer; and a second electrode in contact with an upper surface of the first resistance layer, wherein the first resistance layer includes a first layer and a second layer having an electrical resistivity lower than an electrical resistivity of the first layer, wherein the second layer includes a first portion having a bottom surface that is connected with the first electrode and a second portion having a top surface that is coupled with the second electrode via the first resistance layer, wherein the second portion is separated from the first portion and a bottom surface of the second portion is free of electrical connection. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: a first wire in contact with a lower surface of the first electrode; and a second wire in contact with an upper surface of the second electrode. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the first electrode is in contact with an upper surface of the substrate. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the first electrode is disposed at a position vertically overlapping the first portion, and the second electrode is disposed at a position vertically overlapping the second portion. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the first layer contains a metal element and a silicon element. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the second layer is provided on a lower surface of the first layer. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the second electrode penetrates the first layer. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, wherein the second electrode is in contact with the second layer. ### Claim 9 (depends on 6) The semiconductor device according to claim 6, wherein the second layer has a tapered side surface, and the first layer is in contact with an upper surface and the tapered side surface of the second layer. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, further comprising: a second resistance layer provided on the substrate; a third electrode that is in contact with a lower surface of the second resistance layer and is electrically connected to the second electrode; and a fourth electrode in contact with an upper surface of the second resistance layer. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, further comprising: a first wire in contact with a lower surface of the first electrode; a second wire in contact with an upper surface of the second electrode and a lower surface of the third electrode; and a third wire in contact with an upper surface of the fourth electrode. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein at least one of a set of the second electrode and the second wire or a set of the third electrode and the third wire forms a dual damascene wire. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the first resistance layer is provided between a photoelectric conversion element and a signal processing circuit. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the photoelectric conversion element is provided in the substrate. ### Claim 15 (depends on 13) The semiconductor device according to claim 13, wherein the photoelectric conversion element is a single photon avalanche diode (SPAD). ### Claim 16 (depends on 13) The semiconductor device according to claim 13, wherein the substrate includes a first surface on which the first resistance layer, the first electrode, and the second electrode are provided, and a second surface provided with a lens that allows light to enter the photoelectric conversion element. ### Claim 17 A method for manufacturing a semiconductor device, the method comprising: forming a first electrode on a substrate; forming a first resistance layer in contact with an upper surface of the first electrode; and forming a second electrode in contact with an upper surface of the first resistance layer, wherein the first resistance layer is formed to have a first layer and a second layer having an electrical resistivity lower than an electrical resistivity of the first layer, wherein the second layer is formed to have a first portion having a bottom surface that is connected with the first electrode and a second portion having a top surface that is coupled with the second electrode via the first resistance layer, and wherein the second portion is separated from the first portion and a bottom surface of the second portion is free of electrical connection. ### Claim 18 (depends on 17) The method for manufacturing a semiconductor device according to claim 17, wherein the first electrode is in contact with an upper surface of the substrate. ### Claim 19 (depends on 17) The method for manufacturing a semiconductor device according to claim 17, wherein the first layer contains a metal element and a silicon element.