Image sensor

An image sensor, comprising:

• a first semiconductor chip including
• a first semiconductor substrate having a first region in which a plurality of pixels are arranged and a second region around the first region,
• a first wiring structure on a lower surface of the first semiconductor substrate and having a first wiring layer, and
• a first bonding pad exposed to the lower surface of the first wiring structure and connected to the first wiring layer;
• a second semiconductor chip including
• a second semiconductor substrate having an upper surface on which transistors of a pixel signal generator circuit are located and a lower surface having a recessed portion in a region overlapping the second region,
• a second wiring structure on the upper surface of the second semiconductor substrate, the second wiring structure in contact with the first wiring structure, the second wiring structure having a second wiring layer,
• a second upper bonding pad exposed to an upper surface of the second wiring structure and bonded to the first bonding pad, and
• a via structure connected to the second wiring layer and penetrating through the recessed portion of the second semiconductor substrate, the via structure including
• a via plug, and
• an insulating liner surrounding a side surface of the via plug,
• wherein the via plug includes a protruding portion that is exposed axially and protruding from the insulating liner along a longitudinal axis of the via plug;
• a bonding layer including
• a bonding insulating layer on the lower surface of the second semiconductor substrate and extending to the recessed portion, and
• a second lower bonding pad buried in the bonding insulating layer, the second lower bonding pad exposed to a lower surface of the bonding insulating layer,
• wherein the via plug connects the second wiring layer to the second lower bonding pad,
• wherein the protruding portion of the via plug contacts the second lower bonding pad, such that the second lower bonding pad is connected to the via structure in the recessed portion;
• and
• a third semiconductor chip including
• a third semiconductor substrate having an upper surface on which logic devices are located,
• a third wiring structure on the upper surface of the third semiconductor substrate, the third wiring structure in contact with the bonding insulating layer, the third wiring structure having a third wiring layer, and
• a third bonding pad exposed to an upper surface of the third wiring structure, the third bonding pad bonded to the second lower bonding pad, the third bonding pad connected to the third wiring layer.

An image sensor, comprising:

• a first semiconductor chip including
• a first semiconductor substrate having a first region in which a plurality of pixels are arranged and a second region around the first region,
• a first wiring structure on a lower surface of the first semiconductor substrate and having a first wiring layer, and
• a first bonding pad exposed to a lower surface of the first wiring structure and connected to the first wiring layer;
• a second semiconductor chip including
• a second semiconductor substrate having an upper surface on which transistors of a pixel signal generator circuit are located,
• a second wiring structure on the upper surface of the second semiconductor substrate, the second wiring structure in contact with the first wiring structure, the second wiring structure having a second wiring layer,
• a second upper bonding pad exposed to an upper surface of the second wiring structure and bonded to the first bonding pad, and
• a via structure connected to the second wiring layer, the via structure penetrating through a region of the second semiconductor substrate overlapping the second region of the first semiconductor substrate, the via structure including
• a via plug, and
• an insulating liner surrounding a side surface of the via plug,
• wherein the via plug includes a protruding portion that is exposed axially from and protruding from the insulating liner along a longitudinal axis of the via plug;
• a bonding layer including
• an etching stop layer on the lower surface of the second semiconductor substrate and surrounding an exposed portion of the via structure, the etching stop layer extending in a horizontal plane parallel to the lower surface of the second semiconductor substrate,
• a bonding insulating layer on the etching stop layer, and
• a second lower bonding pad buried in the bonding insulating layer, the second lower bonding pad exposed to a lower surface of the bonding insulating layer,
• wherein the via plug connects the second wiring layer to the second lower bonding pad,
• wherein the protruding portion of the via plug contacts the second lower bonding pad, such that the second lower bonding pad is connected to the via structure;
• and
• a third semiconductor chip including
• a third semiconductor substrate having an upper surface on which logic devices are located,
• a third wiring structure on the upper surface of the third semiconductor substrate, the third wiring structure in contact with the bonding insulating layer, the third wiring structure having a third wiring layer, and
• a third bonding pad exposed to an upper surface of the third wiring structure, the third bonding pad bonded to the second lower bonding pad, the third bonding pad connected to the third wiring layer.