# US 12,765,100 B2 · Image sensor having deep isolation regions

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- Number: US 12,765,100 B2
- Document ID: US12765100B2
- Status: Granted
- Kind: B2
- Application number: 18/183,574
- Filed: 2023-03-14
- Published: 2024-01-25
- Granted: 2026-10-13
- Earliest claimed: 2022-07-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Po Chun Chang; Ping-Hao Lin; Kun-Hui Lin; Kuo-Cheng Lee
- Web page: https://patentgrep.com/patent/US12765100B2

## CPC

- H10F 39/807: {Pixel isolation structures}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A semiconductor structure is disclosed. The semiconductor structure includes a number of pixels and neighboring pixels are isolated by deep trench isolation structures. In an embodiment, a method of forming the semiconductor structure includes epitaxially growing a p-type semiconductor layer on a substrate, epitaxially growing an n-type semiconductor layer over the p-type semiconductor layer, after the epitaxially growing of the n-type semiconductor layer, forming a p-type well in the n-type semiconductor layer, forming an n-type doped region in the n-type semiconductor layer and surrounded by the p-type well, forming a first trench extending through the n-type semiconductor layer and the p-type semiconductor layer and surrounding the p-type well, and forming a first isolation structure in the first trench.

## Claims

### Claim 1

A method, comprising:
epitaxially growing a p-type semiconductor layer on a substrate;
epitaxially growing an n-type semiconductor layer over the p-type semiconductor layer;
after the epitaxially growing of the n-type semiconductor layer, forming a p-type well in the n-type semiconductor layer;
forming an n-type doped floating diffusion region in the n-type semiconductor layer and surrounded by the p-type well;
forming a first trench extending through the n-type semiconductor layer and the p-type semiconductor layer and surrounding the p-type well;
after the forming of the n-type doped floating diffusion region, forming a second trench extending through the p-type well and the n-type doped floating diffusion region; and
forming a first isolation structure in the first trench and a gate structure in the second trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein a depth of the second trench is greater than a depth of the n-type doped floating diffusion region and is less than a depth of the first trench.

### Claim 3 (depends on 2)

The method of claim 2, wherein a depth of the p-type well is greater than the depth of the n-type doped floating diffusion region.

### Claim 4 (depends on 1)

The method of claim 1, wherein, in a top view, the gate structure surrounds the n-type doped floating diffusion region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming of the first isolation structure comprises:
conformally depositing a dielectric liner over the substrate;
depositing a conductive material layer over the dielectric liner; and
performing a planarization process to the dielectric liner and the conductive material layer to expose a top surface of the n-type semiconductor layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the conductive material layer comprises doped polysilicon, tungsten, titanium, or aluminum.

### Claim 7 (depends on 1)

The method of claim 1, wherein a dopant concentration of an upper portion of the n-type semiconductor layer is different than a dopant concentration of a lower portion of the n-type semiconductor layer.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
after the forming of the p-type well in the n-type semiconductor layer, forming a p-type doped region in the n-type semiconductor layer, wherein the p-type doped region is disposed directly under the n-type doped floating diffusion region.

### Claim 9

A method, comprising:
forming an n-type semiconductor layer of a photodiode over a top surface of a substrate;
forming a p well in the n-type semiconductor layer of the photodiode;
forming a floating diffusion region in the n-type semiconductor layer of the photodiode and adjacent the p well, the floating diffusion region being configured to receive charges from the photodiode;
forming an isolation structure extending through the p well and the n-type semiconductor layer of the photodiode; and
forming a gate structure extending through the floating diffusion region without extending through the n-type semiconductor layer of the photodiode, wherein the gate structure is disposed between the p well and the floating diffusion region,
wherein, in a top view, the gate structure surrounds the floating diffusion region.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
epitaxially forming a p-type semiconductor layer on the top surface of the substrate, wherein the n-type semiconductor layer of the photodiode is spaced apart from the substrate by the p-type semiconductor layer.

### Claim 11 (depends on 9)

The method of claim 9, wherein the forming of the n-type semiconductor layer comprises epitaxially forming an in-situ doped n-type semiconductor layer over the top surface of the substrate, wherein a dopant concentration of an upper portion of the n-type semiconductor layer is different than a dopant concentration of a lower portion of the n-type semiconductor layer.

### Claim 12 (depends on 9)

The method of claim 9, wherein the forming of the isolation structure comprises:
performing a first etching process to form a first trench extending through the p well and the n-type semiconductor layer of the photodiode;
conformally depositing a dielectric liner over the substrate and in the first trench;
depositing a conductive material layer over the dielectric liner and in the first trench; and
performing a planarization process to the dielectric liner and the conductive material layer to expose a top surface of the n-type semiconductor layer.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
performing a planarization process to a bottom surface of the substrate to expose the conductive material layer, the bottom surface of the substrate being opposite to the top surface of the substrate; and
forming a color filter under the photodiode.

### Claim 14 (depends on 12)

The method of claim 12, wherein the forming of the gate structure comprises:
performing a second etching process to form a second trench separating the p well and the floating diffusion region,
wherein the conformally depositing of the dielectric liner further partially fills the second trench, and the depositing of the conductive material layer further fills a remaining portion of the second trench.

### Claim 15 (depends on 9)

The method of claim 9, wherein a bottom surface of the gate structure is below the floating diffusion region.

### Claim 16 (depends on 9)

The method of claim 9, wherein a dopant concentration of the floating diffusion region is greater than a dopant concentration of the p well.

### Claim 17

A method, comprising:
epitaxially growing an n-type semiconductor layer over a substrate;
forming a p-type well in the n-type semiconductor layer, wherein the p-type well extends from a top surface of the n-type semiconductor layer into the n-type semiconductor layer;
forming an n-type doped region in the n-type semiconductor layer and surrounded by the p-type well;
forming a first trench extending through the n-type semiconductor layer and a second trench separating the n-type doped region and the p-type well;
depositing a dielectric layer in the first trench and the second trench; and
depositing a conductive layer over the dielectric layer and in the first trench and the second trench, thereby forming a first feature in the first trench and a second feature in the second trench,
wherein, in a top view, the first feature surrounds the p-type well, and the second feature surrounds the n-type doped region.

### Claim 18 (depends on 17)

The method of claim 17, wherein a depth of the first feature is greater than a depth of the second feature, and the depth of the second feature is greater than a depth of the p-type well and the n-type doped region.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
forming an interconnect structure over the first feature and the second feature;
planarizing the substrate from its back to expose the conductive layer of the first feature; and
forming color filters under the n-type semiconductor layer and the first feature.

### Claim 20 (depends on 17)

The method of claim 17, wherein the p-type well laterally extends from the first feature to the second feature.