# US 12,765,083 B2 · Image sensing structure and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,083 B2 - Document ID: US12765083B2 - Status: Granted - Kind: B2 - Application number: 18/150,806 - Filed: 2023-01-06 - Published: 2024-03-21 - Granted: 2026-10-13 - Earliest claimed: 2022-09-16 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Feng-Chien Hsieh; Yun-Wei Cheng; Wei-Li Hu; Kuo-Cheng Lee; Cheng-Ming Wu - Web page: https://patentgrep.com/patent/US12765083B2 ## CPC - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10F 39/8027: {Geometry of the photosensitive area} - H10F 39/014: {of CMOS image sensors} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract The image sensing structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes at least one first unit. The at least one first unit includes a plurality of first interconnects adjacent to the top side of the first semiconductor device, a row selector, and an analog-to-digital converter (ADC) connected to the row selectors. The second semiconductor device includes at least one second unit. The at least one second unit includes a photodiode facing the top side of the second semiconductor device. The photodiode is configured to receive the light incident on the top side of the second semiconductor device. The top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device. ## Claims ### Claim 1 An image sensing structure comprising: a first semiconductor device comprising: a top side; a bottom side opposite to the top side of the first semiconductor device; and at least one first unit comprising: a plurality of first interconnects adjacent to the top side of the first semiconductor device; a row selector; and an analog-to-digital converter (ADC) connected to the row selector, wherein the ADC directly contacts a first conductive via of the plurality of first interconnects and the row selector directly contacts a second conductive via of the plurality of first interconnects, and the first conductive via and the second conductive via directly contact and are electrically connected to a conductive structure of the plurality of first interconnects; and a second semiconductor device disposed on the first semiconductor device, the second semiconductor device comprising: a top side; a bottom side opposite to the top side of the second semiconductor device and facing the top side of the first semiconductor device; and at least one second unit comprising: a photodiode facing the top side of the second semiconductor device and configured to receive the light incident on the top side of the second semiconductor device, wherein the top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device; a transfer gate configured to transmit charges stored in the photodiode to a sensing node; and a source follower configured to amplify a voltage of the sensing node; wherein the second semiconductor device includes a photo sensor chip and the first semiconductor device includes an application specific integrated circuit (ASIC) chip, wherein light signals generated by the photodiode of the at least one second unit are directly transmitted to the row selector of the at least one first unit through a pixel level hybrid bonding at an interface between the top side of the first semiconductor device and the bottom side of the second semiconductor device, wherein the pixel level hybrid bonding includes a lower conductive structure disposed in the first semiconductor device and an upper conductive structure disposed in the second semiconductor device, wherein a top surface of the lower conductive structure directly contacts and is electrically connected to a bottom surface of the upper conductive structure, wherein the row selector selects a corresponding row for selecting a signal during a time period at a level in accordance with the voltage of the sensing node charged with an output current from the photodiode. ### Claim 2 (depends on 1) The image sensing structure of claim 1, wherein the top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device through the pixel level hybrid bonding such that one first unit of the first semiconductor device corresponds to one or more second units of the second semiconductor device. ### Claim 3 (depends on 1) The image sensing structure of claim 1, wherein the ADC is directly electrically connected to the photodiode of the at least one second unit through the row selector and the pixel level hybrid bonding for immediate signal transfer. ### Claim 4 (depends on 1) The image sensing structure of claim 1, wherein the at least one first unit further comprises a plurality of three dimension (3D) metal insulator metal (MIM) structures. ### Claim 5 (depends on 4) The image sensing structure of claim 4, wherein the plurality of 3D MIM structures are configured to store signals detected by the photodiode. ### Claim 6 (depends on 5) The image sensing structure of claim 5, wherein the light signals generated by the photodiode of the at least one second unit are correspondingly transmitted to the ADC of the at least one first unit through the plurality of first interconnects. ### Claim 7 (depends on 1) The image sensing structure of claim 1, wherein the pixel level hybrid bonding is a pixel-level joint of the at least one first unit and the at least one second unit. ### Claim 8 (depends on 1) The image sensing structure of claim 1, wherein the transfer gate is configured as a CMOS switch. ### Claim 9 (depends on 8) The image sensing structure of claim 8, wherein the at least one second unit of the second semiconductor device further comprises a reset transistor connected to the transfer gate, wherein the reset transistor and the transfer gate share a common n-plus doped region disposed between the reset transistor and the transfer gate. ### Claim 10 (depends on 9) The image sensing structure of claim 9, wherein the source follower and the reset transistor share a common n-plus doped region disposed between the source follower and the reset transistor. ### Claim 11 An image sensing structure comprising: a first semiconductor device comprising: a top side; a bottom side opposite to the top side of the first semiconductor device; and a plurality of first units, each of the plurality of first units comprising: a plurality of first interconnects adjacent to the top side of the first semiconductor device; and a row selector connected to the plurality of first interconnects; and an analog-to-digital converter (ADC), wherein the ADC directly contacts a first conductive via of the plurality of first interconnects and the row selector directly contacts a second conductive via of the plurality of first interconnects, and the first conductive via and the second conductive via directly contact and are electrically connected to a conductive structure of the plurality of first interconnects; a second semiconductor device disposed on the first semiconductor device, the second semiconductor device comprising: a top side; a bottom side opposite to the top side of the second semiconductor device and facing the top side of the first semiconductor device; and at least one second unit comprising: a photodiode adjacent to the top side of the second semiconductor device and configured to receive the light incident on the top side of the second semiconductor device; a transfer gate configured to transmit charges stored in the photodiode to a sensing node; and a source follower configured to amplify a voltage of the sensing node; wherein the top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device, wherein the second semiconductor device includes a photo sensor chip and the first semiconductor device includes an application specific integrated circuit (ASIC) chip, wherein light signals generated by the photodiode of the at least one second unit are directly transmitted to the row selector of one of the plurality of first units through a pixel level hybrid bonding at an interface between the top side of the first semiconductor device and the bottom side of the second semiconductor device, wherein the pixel level hybrid bonding includes a lower conductive structure disposed in the first semiconductor device and an upper conductive structure disposed in the second semiconductor device, wherein a top surface of the lower conductive structure directly contacts and is electrically connected to a bottom surface of the upper conductive structure, wherein the row selector selects a corresponding row for selecting a signal during a time period at a level in accordance with the voltage of the sensing node charged with an output current from the photodiode. ### Claim 12 (depends on 11) The image sensing structure of claim 11, wherein the bottom side of the second semiconductor device is bonded to the top side of the first semiconductor device through the pixel level hybrid bonding. ### Claim 13 (depends on 11) The image sensing structure of claim 11, wherein the ADC is directly electrically connected to the photodiode of the at least one second unit through the pixel level hybrid bonding for immediate signal transfer. ### Claim 14 (depends on 11) The image sensing structure of claim 11, wherein the each of the plurality of first units further comprises a plurality of three dimension (3D) metal insulator metal (MIM) structures. ### Claim 15 (depends on 14) The image sensing structure of claim 14, wherein the plurality of 3D MIM structures are configured to store signals detected by the photodiode. ### Claim 16 (depends on 15) The image sensing structure of claim 15, wherein light signals generated by the photodiode are correspondingly transmitted to the ADC through the plurality of first interconnects. ### Claim 17 (depends on 11) The image sensing structure of claim 11, wherein the transfer gate is configured as a CMOS switch. ### Claim 18 An image sensing structure comprising: a first semiconductor device comprising: a top side; a bottom side; and at least one first unit comprising: a plurality of first interconnects adjacent to the top side of the first semiconductor device; a row selector electrically connected to the plurality of first interconnects; and an analog-to-digital converter (ADC) electrically connected to the row selector through the plurality of first interconnects, wherein the ADC directly contacts a first conductive via of the plurality of first interconnects and the row selector directly contacts a second conductive via of the plurality of first interconnects, and the first conductive via and the second conductive via directly contact and are electrically connected to a conductive structure of the plurality of first interconnects; and a second semiconductor device disposed on the first semiconductor device, the second semiconductor device comprising: a top side; a bottom side facing the top side of the first semiconductor device; and at least one second unit comprising: a photodiode disposed in the second semiconductor device and configured to receive the light incident on the top side of the second semiconductor device; a transfer gate configured to transmit charges stored in the photodiode to a sensing node; and a source follower configured to amplify a voltage of the sensing node; wherein the top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device through a pixel level hybrid bonding such that one first unit of the first semiconductor device corresponds to one or more second units of the second semiconductor device, wherein the second semiconductor device includes a photo sensor chip and the first semiconductor device includes an application specific integrated circuit (ASIC) chip, wherein light signals generated by the photodiode of the at least one second unit are directly transmitted to the row selector of the at least one first unit through a pixel level hybrid bonding at an interface between the top side of the first semiconductor device and the bottom side of the second semiconductor device, wherein the row selector of the at least one first unit is directly electrically connected to the photodiode of the at least one second unit to control the light signals from the photodiode, wherein the pixel level hybrid bonding includes a lower conductive structure disposed in the first semiconductor device and an upper conductive structure disposed in the second semiconductor device, wherein a top surface of the lower conductive structure directly contacts and is electrically connected to a bottom surface of the upper conductive structure, wherein the row selector selects a corresponding row for selecting a signal during the time period at a level in accordance with the voltage of the sensing node charged with an output current from the photodiode. ### Claim 19 (depends on 18) The image sensing structure of claim 18, wherein the transfer gate is configured as a CMOS switch. ### Claim 20 (depends on 18) The image sensing structure of claim 18, wherein the at least one first unit further comprises a plurality of three dimension (3D) metal insulator metal (MIM) structures.