# US 12,765,074 B2 · Semiconductor device and method for fabricating the same

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- Number: US 12,765,074 B2
- Document ID: US12765074B2
- Status: Granted
- Kind: B2
- Application number: 18/772,301
- Filed: 2024-07-15
- Published: 2024-11-07
- Granted: 2026-10-13
- Earliest claimed: 2021-12-17
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chih-Kai Hsu; Ssu-I Fu; Yu-Hsiang Lin; Chien-Ting Lin; Chia-Jung Hsu; Chun-Ya Chiu; Chin-Hung Chen
- Web page: https://patentgrep.com/patent/US12765074B2

## CPC

- H10D 89/811: {using FETs as protective elements}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, a HV device on the HV region, and a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region;
a HV device on the HV region, wherein the HV device comprises:
a first base on the substrate;
a first gate dielectric layer on the first base;
a first gate electrode on the first gate dielectric layer, wherein the first gate electrode comprises a metal gate;
a LV device on the LV region, wherein the LV device comprises:
a fin-shaped structure on the substrate;
a second gate electrode on the fin-shaped structure, wherein a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the first gate electrode is even with a top surface of the second gate electrode.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the HV device comprises a source/drain region adjacent to the first gate electrode, wherein a top surface of the source/drain region is even with the top surface of the fin-shaped structure.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising a shallow trench isolation (STI) between the first base and the source/drain region.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, further comprising an electrostatic discharge (ESD) protection ring around the HV device.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein a top surface of the ESD protection ring is even with the top surface of the source/drain region.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a MV device on the MV region, wherein the MV device comprises:
a second base on the substrate;
a second gate dielectric layer on the second base; and
a third gate electrode on the second gate dielectric layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein a top surface of the first gate dielectric layer is lower than the top surface of the second gate dielectric layer.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein a top surface of the first gate electrode is even with a top surface of the third gate electrode.