Semiconductor device

A semiconductor memory device comprising:

• a memory cell array;
• a first pad through which a first power supply voltage for operating the memory cell array is to be supplied;
• a second pad through which a second power supply voltage for operating the memory cell array is to be supplied;
• a third pad through which a ground voltage is to be supplied;
• a protection circuit between the first and third pads, wherein the protection circuit includes
• a plurality of first transistors arranged in a first direction and formed on a well region of a first conductivity type,
• a plurality of second transistors arranged in the first direction, formed on the well region of the first conductivity type, and disposed apart from the first transistors in a second direction orthogonal to the first direction,
• an outer guard ring in direct contact with the well region of the first conductivity type and provided around the plurality of first transistors and the plurality of second transistors, and
• an intermediate guard ring in direct contact with the well region of the first conductivity type, provided between the plurality of first transistors and the plurality of second transistors, and connected to the third pad via a resistance element.