# US 12,765,069 B2 · Small dummy poly pattern insertion in small border regions

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- Number: US 12,765,069 B2
- Document ID: US12765069B2
- Status: Granted
- Kind: B2
- Application number: 18/349,965
- Filed: 2023-07-11
- Published: 2025-01-16
- Granted: 2026-10-13
- Earliest claimed: 2023-07-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Anhao Cheng; Ke-Jing Yu; Meng-I Kang; Yen-Liang Lin; Ching Lee; Pi-Tzu Chen
- Web page: https://patentgrep.com/patent/US12765069B2

## CPC

- H10D 89/10: Integrated device layouts
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- H10P 52/403: {of conductive or resistive materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method is provided. The method includes the following steps: identifying a first intellectual property (IP) block and a second IP block in an integrated circuit; identifying a small border region between the first IP block and the second IP block, wherein the small border region has a width in a first horizontal direction, and the width is between a small border region dimension lower limit and a small border region dimension upper limit; and inserting at least one small dummy gate feature pattern in the small border region.

## Claims

### Claim 1

A method comprising:
identifying a first intellectual property (IP) block and a second IP block in an integrated circuit;
identifying a small border region between the first IP block and the second IP block, wherein the small border region has a width in a first horizontal direction, and the width is between a small border region dimension lower limit and a small border region dimension upper limit; and
inserting at least one small dummy gate feature pattern in the small border region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the small border region dimension upper limit is 3.6 μm.

### Claim 3 (depends on 2)

The method of claim 2, wherein the small border region dimension lower limit is 0.5 μm.

### Claim 4 (depends on 1)

The method of claim 1, wherein the at least one small dummy gate feature pattern includes a plurality of small dummy gate feature patterns.

### Claim 5 (depends on 4)

The method of claim 4, wherein the plurality of small dummy gate feature patterns are organized in an array.

### Claim 6 (depends on 4)

The method of claim 4, wherein each of the plurality of small dummy gate feature patterns has a width in the first horizontal direction between 0.01 μm and 0.2 μm and a length in a second horizontal direction perpendicular to the first horizontal direction between 0.1 μm and 0.5 μm.

### Claim 7 (depends on 6)

The method of claim 6, wherein a distance in the first horizontal direction between two neighboring small dummy gate feature patterns of the plurality of small dummy gate feature patterns is between 0.05 μm and 0.2 μm.

### Claim 8 (depends on 6)

The method of claim 6, wherein a distance in the second horizontal direction between two neighboring small dummy gate feature patterns of the plurality of small dummy gate feature patterns is between 0.05 μm and 0.2 μm.

### Claim 9 (depends on 4)

The method of claim 4, wherein each of the plurality of small dummy gate feature patterns has a width in the first horizontal direction between 0.1 μm and 0.5 μm and a length in a second horizontal direction perpendicular to the first horizontal direction between 0.01 μm and 0.2 μm.

### Claim 10 (depends on 1)

The method of claim 1 further comprising:
scanning the small border region for a design rule check (DRC) violation.

### Claim 11 (depends on 10)

The method of claim 10 further comprising:
inserting at least one additional small dummy gate feature pattern in the small border region when the DRC violation is detected.

### Claim 12

A method comprising:
identifying a plurality of intellectual property (IP) blocks in an integrated circuit;
identifying border regions in the integrated circuit, the border regions being outside the plurality of IP blocks and including at least one small border region and at least one large border region, wherein the small border region has a width in a first horizontal direction and a length in a second horizontal direction perpendicular to the first horizontal direction, and at least one of the width and the length is between a small border region dimension lower limit and a small border region dimension upper limit; and
inserting at least one small dummy gate feature pattern in the at least one small border region.

### Claim 13 (depends on 12)

The method of claim 12 further comprising:
inserting at least one large dummy gate feature pattern in the at least one large border region.

### Claim 14 (depends on 13)

The method of claim 13 further comprising:
scanning the at least one small border region for a design rule check (DRC) violation.

### Claim 15 (depends on 14)

The method of claim 14, wherein the scanning comprises:
scanning the at least one small border region using a vertical rectangular area;
scanning the at least one small border region using a horizontal rectangular area; and
identifying a position of the vertical rectangular area or the horizontal rectangular area where not any small dummy POLY patterns overlap with the vertical rectangular area or the horizontal rectangular area, respectively.

### Claim 16 (depends on 15)

The method of claim 15 further comprising:
inserting at least one additional small dummy gate feature pattern in the identified position.

### Claim 17 (depends on 15)

The method of claim 15, wherein the vertical rectangular area has a width in the first horizontal direction of 0.5 μm and a length in the second horizontal direction of 10 μm, and the horizontal rectangular area has a width in the first horizontal direction of 10 μm and a length in the second horizontal direction of 0.5 μm.

### Claim 18

An integrated circuit (IC) comprising:
a substrate;
a first intellectual property (IP) block fabricated on the substrate;
a second IP block fabricated on the substrate;
a small border region between the first IP block and the second IP block, wherein the small border region has a width in a first horizontal direction, and the width is between a small border region dimension lower limit and a small border region dimension upper limit; and
at least one small dummy gate feature pattern disposed in the small border region.

### Claim 19 (depends on 18)

The integrated circuit of claim 18, wherein the small border region dimension upper limit is 3.6 μm, and wherein the small border region dimension lower limit is 0.5 μm.

### Claim 20 (depends on 19)

The integrated circuit of claim 19, wherein the small dummy gate feature pattern has a width in the first horizontal direction between 0.01 μm and 0.2 μm and a length in a second horizontal direction perpendicular to the first horizontal direction between 0.1 μm and 0.5 μm.