# US 12,765,067 B2 · Method for manufacturing high-voltage transistors on a silicon-on-insulator type bulk > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,067 B2 - Document ID: US12765067B2 - Status: Granted - Kind: B2 - Application number: 18/343,298 - Filed: 2023-06-28 - Published: 2024-01-11 - Granted: 2026-10-13 - Earliest claimed: 2022-07-06 - Assignees: STMicroelectronics (Crolles 2) SAS - Applicants: STMicroelectronics (Crolles 2) SAS - Inventors: Alexandre Villaret; Olivier Weber; Franck Arnaud - Web page: https://patentgrep.com/patent/US12765067B2 ## CPC - H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate - H10D 30/637: {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs} - H10D 86/01: Manufacture or treatment - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method can be used for manufacturing a high-voltage transistor in and on a high-voltage region of a silicon-on-insulator type bulk that includes a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer. The semiconductor film in the high-voltage region is selectively epitaxially grown to a second thickness that is greater than the first thickness while the semiconductor film remains at the first thickness in a region outside the high-voltage region. ## Claims ### Claim 1 A method for manufacturing a high-voltage transistor in and on a high-voltage region of a silicon-on-insulator type bulk including a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer, the method comprising: selectively epitaxially growing the semiconductor film in the high-voltage region to a second thickness that is greater than the first thickness, the semiconductor film remaining at the first thickness in a region outside the high-voltage region; and epitaxially growing the carrier bulk in a localized monolithic region of the silicon-on-insulator type bulk, wherein the epitaxially growing of the semiconductor film in the high-voltage region is performed simultaneously with the epitaxially growing of the carrier bulk in the localized monolithic region, wherein epitaxially growing the carrier bulk in the localized monolithic region comprises: forming a hard mask comprising a high-voltage mask portion and a first opening, the high-voltage mask portion covering the semiconductor film in the high-voltage region and the first opening uncovering the semiconductor film in the localized monolithic region; oxidizing the semiconductor film in the localized monolithic region at the first opening; and selectively etching to remove the oxidized semiconductor film and the buried dielectric layer in the localized monolithic region. ### Claim 2 (depends on 1) The method according to claim 1, wherein epitaxially growing the semiconductor film in the high-voltage region comprises etching to remove the high-voltage mask portion of the hard mask in the high-voltage region prior to the epitaxially growing of the semiconductor film in the high-voltage region. ### Claim 3 (depends on 1) The method according to claim 1, further comprising: forming a gate region of the high-voltage transistor on the semiconductor film having the second thickness of the high-voltage region; and forming conduction regions of the high-voltage transistor in the semiconductor film having the second thickness of the high-voltage region. ### Claim 4 (depends on 3) The method according to claim 3, wherein the second thickness of the semiconductor film in the high-voltage region is configured to generate a fully depleted state throughout the thickness of the semiconductor film in the presence of a channel region of the high-voltage transistor. ### Claim 5 (depends on 1) The method according to claim 1, wherein the second thickness is at least 13 nm greater than the first thickness. ### Claim 6 (depends on 1) The method according to claim 1, wherein the first thickness is less than or equal to 7 nm. ### Claim 7 A method of manufacturing a semiconductor device, comprising: forming a hard mask on a silicon-on-insulator type bulk, wherein the silicon-on-insulator type bulk comprises a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer, the hard mask comprising a high-voltage mask portion covering the semiconductor film in a high-voltage region and also comprising a first opening uncovering the semiconductor film in a localized monolithic region; oxidizing the semiconductor film in the localized monolithic region; selectively etching to remove the oxidized semiconductor film and the buried dielectric layer at the first opening in the localized monolithic region; etching selectively the hard mask to remove the high-voltage mask portion, such that the hard mask comprises a second opening uncovering the semiconductor film in the high-voltage region; epitaxially growing the semiconductor film to a second thickness at the second opening in the high-voltage region, such that the second thickness is at least 13 nm greater than the first thickness; and epitaxially growing the carrier bulk in the localized monolithic region simultaneously with the epitaxially growing of the semiconductor film. ### Claim 8 (depends on 7) The method according to claim 7, further comprising forming a high-voltage transistor on the semiconductor film of the high-voltage region, forming the high-voltage transistor comprising: forming a gate channel region of the high-voltage transistor on the semiconductor film having the second thickness of the high-voltage region; and forming source and drain regions of the high-voltage transistor in the semiconductor film having at least the second thickness of the high-voltage region. ### Claim 9 (depends on 7) The method of claim 7, wherein the first thickness is less than or equal to 7 nm and the second thickness is between 20 nm and 25 nm. ### Claim 10 (depends on 1) The method according to claim 1, wherein the second thickness is between 20 nm and 25 nm. ### Claim 11 (depends on 7) The method according to claim 7, wherein the second thickness is less than or equal to 25 nm. ### Claim 12 A method of manufacturing a semiconductor device on a silicon-on-insulator type bulk comprising a semiconductor film having a first thickness electrically insulated from a carrier bulk by a buried dielectric layer, the method comprising: forming a hard mask on the silicon-on-insulator type bulk, the hard mask covering the semiconductor film in a low-voltage region and in a high-voltage region while uncovering the semiconductor film in a localized monolithic region; oxidizing the semiconductor film in the localized monolithic region; selectively etching to remove the oxidized semiconductor film and the buried dielectric layer in the localized monolithic region to expose the carrier bulk; etching the hard mask to remove the hard mask from the high-voltage region while the hard mask remains covering the semiconductor film in the low-voltage region; epitaxially growing the semiconductor film in the high-voltage region to a second thickness less than 25 nm simultaneously with epitaxially growing the carrier bulk in the localized monolithic region, the semiconductor film remaining at the first thickness in the low-voltage region throughout; forming a high-voltage transistor in and on the semiconductor film having the second thickness in the high-voltage region; forming a low-voltage transistor in and on the semiconductor film having the first thickness in the low-voltage region; and forming a transistor in and on the epitaxially grown carrier bulk in the localized monolithic region. ### Claim 13 (depends on 12) The method according to claim 12, wherein the first thickness is less than or equal to 7 nm. ### Claim 14 (depends on 13) The method according to claim 13, wherein the second thickness is between 20 nm and 25 nm. ### Claim 15 (depends on 12) The method according to claim 12, wherein the second thickness is at least 13 nm greater than the first thickness. ### Claim 16 (depends on 12) The method according to claim 12, wherein the second thickness of the semiconductor film in the high-voltage region is configured to generate a fully depleted state throughout the thickness of the semiconductor film in the presence of a channel region of the high-voltage transistor. ### Claim 17 (depends on 12) The method according to claim 12, wherein forming the hard mask comprises forming a silicon nitride mask, and wherein etching the hard mask to remove the hard mask from the high-voltage region comprises selectively etching the silicon nitride mask such that the silicon nitride mask is removed from the high-voltage region while remaining over the semiconductor film in the low-voltage region. ### Claim 18 (depends on 12) The method according to claim 12, wherein forming the high-voltage transistor comprises: forming a gate region of the high-voltage transistor on the semiconductor film having the second thickness in the high-voltage region; and forming source and drain regions of the high-voltage transistor in the semiconductor film having the second thickness in the high-voltage region. ### Claim 19 (depends on 12) The method according to claim 12, wherein the high-voltage transistor is designed to operate at a voltage between 2 volts and 5 volts, and the low-voltage transistor is designed to operate at a voltage below 2 volts. ### Claim 20 (depends on 12) The method according to claim 12, wherein epitaxially growing the carrier bulk in the localized monolithic region is performed such that a top surface of the epitaxially grown carrier bulk in the localized monolithic region is substantially coplanar with a top surface of the semiconductor film in the low-voltage region.