# US 12,765,063 B2 · Display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,063 B2 - Document ID: US12765063B2 - Status: Granted - Kind: B2 - Application number: 18/363,937 - Filed: 2023-08-02 - Published: 2024-04-11 - Granted: 2026-10-13 - Earliest claimed: 2022-10-11 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., LTD. - Inventors: Hae Min Kim; Young Wan Seo; Geun Ho Lee; Kyung Hoon Chung - Web page: https://patentgrep.com/patent/US12765063B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10W 90/00: Package configurations - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A display device comprises a display area comprising a plurality of pixels, and a data line and a gate line electrically connected to the plurality of pixels, a non-display area disposed adjacent to the display area, a plurality of pads disposed on a side of the non-display area, a gate control line electrically connected to at least one of the plurality of pads and that supplies a gate control signal, a driving voltage line electrically connected to at least one of the plurality of pads and that supplies a driving voltage, an antistatic circuit electrically connected to the gate control line, a scan driver that generates a gate signal based on a gate control signal received from the gate control line and that supplies the gate signal to the gate line, and a shielding layer integral to the driving voltage line to overlap the top of the antistatic circuit. ## Claims ### Claim 1 A display device, comprising: a display area comprising: a plurality of pixels; and a data line and a gate line that are electrically connected to the plurality of pixels; a non-display area disposed adjacent to the display area; a plurality of pads disposed on a side of the non-display area; a gate control line that is electrically connected to at least one first pad of the plurality of pads and that supplies a gate control signal; a driving voltage line that is electrically connected to at least one second pad of the plurality of pads and that supplies a driving voltage; an antistatic circuit electrically connected to the gate control line; a scan driver that generates a gate signal based on a gate control signal received from the gate control line and that supplies the gate signal to the gate line; and a shielding layer integral to the driving voltage line to overlap the top of the antistatic circuit. ### Claim 2 (depends on 1) The display device of claim 1, wherein the antistatic circuit comprises a transistor comprising an oxide-based semiconductor region. ### Claim 3 (depends on 2) The display device of claim 2, wherein the shielding layer includes a plurality of holes that do not overlap a semiconductor region of the transistor. ### Claim 4 (depends on 1) The display device of claim 1, further comprising: a low potential line that is electrically connected to at least one third pad of the plurality of pads and that supplies a low potential voltage, wherein the shielding layer is integral to the low potential line to overlap the top of the antistatic circuit. ### Claim 5 (depends on 1) The display device of claim 1, further comprising: a gate high voltage line that is electrically connected to at least one fourth pad of the plurality of pads and that supplies a gate high voltage; a first gate low voltage line that is electrically connected to at least one fifth pad of the plurality of pads and that supplies a first gate low voltage; and a second gate low voltage line that is electrically connected to at least one sixth pad of the plurality of pads and that supplies a second gate low voltage lower than the first gate low voltage. ### Claim 6 (depends on 5) The display device of claim 5, wherein the antistatic circuit comprises: a first transistor electrically connected between the gate high voltage line and the gate control line; a second transistor electrically connected between the gate control line and the first gate low voltage line; a first resistance line electrically connected between a gate electrode of the first transistor and the gate control line; and a second resistance line electrically connected between a gate electrode of the second transistor and the first gate low voltage line. ### Claim 7 (depends on 6) The display device of claim 6, wherein the first transistor comprises a first bias electrode electrically connected to the second gate low voltage line to overlap the semiconductor region of the first transistor, and the second transistor comprises a second bias electrode electrically connected to the second gate low voltage line to overlap the semiconductor region of the second transistor. ### Claim 8 (depends on 5) The display device of claim 5, wherein the shielding layer overlaps a portion of each of the gate high voltage line, and the first and second gate low voltage lines, and the shielding layer includes a plurality of holes that overlap another portion of each of the gate high voltage line, and the first and second gate low voltage lines. ### Claim 9 (depends on 1) The display device of claim 1, further comprising: a DC electrode that is electrically connected to at least one seventh pad of the plurality of pads and that supplies a DC voltage; a test signal line that is electrically connected to at least one eighth pad of the plurality of pads and that supplies a test gate signal; and a test transistor that supplies the DC voltage based on the test gate signal to the data lines, wherein the DC electrode overlaps a semiconductor region of the test transistor. ### Claim 10 (depends on 9) The display device of claim 9, wherein the test transistor comprises: a drain electrode overlapping the DC electrode and electrically connected to the DC electrode; a gate electrode receiving the test gate signal and overlapping a semiconductor region of the test transistor; and a source electrode electrically connected to the data line. ### Claim 11 A display device, comprising: a substrate; a display area comprising: a plurality of pixels; and a data line and a gate line that are electrically connected to the plurality of pixels disposed on the substrate; a non-display area disposed adjacent to the display area; a plurality of pads disposed on a side of the non-display area, a gate control line that is electrically connected to at least one first pad of the plurality of pads and that supplies a gate control signal; an antistatic circuit that is electrically connected to the gate control line and that comprises a transistor and a resistance line; a driving voltage line that is electrically connected to at least one second pad of the plurality of pads and that supplies a driving voltage; a shielding layer integral to the driving voltage line to overlap the transistor and the resistance line, wherein a bias electrode of the transistor is disposed in a first metal layer of the substrate, a semiconductor region of the transistor is disposed in an active layer on the first metal layer, a gate electrode of the transistor is disposed in a second metal layer on the active layer, the resistance line is disposed in a third metal layer on the second metal layer, the gate control line is disposed in a fourth metal layer on the third metal layer, and the driving voltage line and the shielding layer are disposed in a fifth metal layer on the fourth metal layer. ### Claim 12 (depends on 11) The display device of claim 11, wherein the transistor comprises an oxide-based semiconductor region, and the shielding layer overlaps the semiconductor region of the transistor. ### Claim 13 (depends on 12) The display device of claim 12, wherein the shielding layer comprises a plurality of holes that do not overlap the semiconductor region of the transistor. ### Claim 14 (depends on 11) The display device of claim 11, further comprising: a low potential line that is disposed in the fifth metal layer, that is electrically connected to at least one third pad of the plurality of pads, and that supplies a low potential voltage, wherein the shielding layer is integral to the low potential line to overlap the top of the antistatic circuit. ### Claim 15 (depends on 11) The display device of claim 11, further comprising: a gate high voltage line that is electrically connected to at least one foruth pad of the plurality of pads and that supplies a gate high voltage; a first gate low voltage line that is electrically connected to at least one fifth pad of the plurality of pads and that supplies a first gate low voltage; and a second gate low voltage line that is electrically connected to a sixth pad and that supplies a second gate low voltage lower than the first gate low voltage. ### Claim 16 (depends on 15) The display device of claim 15, wherein each of the gate high voltage, and the first and second gate low voltage lines comprise: a vertical portion disposed in the fourth metal layer to be electrically connected to at least one seventh pad of the plurality of pads; and a horizontal portion disposed in the second metal layer to be electrically connected to the antistatic circuit. ### Claim 17 (depends on 15) The display device of claim 15, wherein the shielding layer overlaps a portion of each of the gate high voltage line, and the first and second low voltage lines, and the plurality of holes of the shielding layer overlap another portion of each of the gate high voltage line, and the first and second gate low voltage lines. ### Claim 18 An electronic device, comprising: a display area comprising: a plurality of pixels; and a data line and a gate line that are electrically connected to the plurality of pixels; a non-display area disposed adjacent to the display area; a plurality of pads disposed on a side of the non-display area; a gate control line that is electrically connected to at least one of the plurality of pads and that supplies a gate control signal; a driving voltage line that is electrically connected to at least one of the plurality of pads and that supplies a driving voltage, an antistatic circuit electrically connected to the gate control line; a scan driver that generates a gate signal based on a gate control signal received from the gate control line and that supplies the gate signal to the gate line; and a shielding layer integral to the driving voltage line to overlap the top of the antistatic circuit. ### Claim 19 (depends on 18) The electronic device of claim 18, wherein: the antistatic circuit comprises a transistor comprising an oxide-based semiconductor region, the driving voltage being a high potential voltage that drives light emitting elements in the display area, and the semiconductor region being a portion of an active layer disposed between a source electrode and a drain electrode. ### Claim 20 (depends on 18) The electronic device of claim 18, further comprising: a DC electrode that is electrically connected to at least one of the plurality of pads and that supplies a DC voltage; a test signal line that is electrically connected to at least one of the plurality of pads and that supplies a test gate signal; and a test transistor that supplies the DC voltage based on the test gate signal to the data lines, wherein the DC electrode overlaps a semiconductor region of the test transistor.