# US 12,765,058 B2 · Gate-all-around devices with different gate oxide thicknesses > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,058 B2 - Document ID: US12765058B2 - Status: Granted - Kind: B2 - Application number: 18/074,814 - Filed: 2022-12-05 - Published: 2024-06-06 - Granted: 2026-10-13 - Earliest claimed: 2022-12-05 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Hwichan Jun; Guillaume Bouche - Web page: https://patentgrep.com/patent/US12765058B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - H10D 84/0142: {the gate conductors having different shapes or dimensions} - H10D 84/0144: {Manufacturing their gate insulating layers} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/431: {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Techniques are provided herein to form semiconductor devices having different gate oxide thicknesses. A first semiconductor device includes a first gate structure around a first plurality of semiconductor nanoribbons and a second semiconductor device includes a second gate structure around a second plurality of semiconductor nanoribbons. The first gate structure includes at least a first gate oxide layer and a first gate electrode, and the second gate structure includes at least a second gate oxide layer and a second gate electrode. The first gate oxide layer is thicker than the second gate oxide layer. A high-k dielectric layer may be formed over the first and second gate oxide layers or may be formed over the second gate oxide layer, but not over the first gate oxide layer. ## Claims ### Claim 1 An integrated circuit comprising: a first semiconductor device having a first plurality of semiconductor bodies extending in a first direction between a first source region and a first drain region, and a first gate structure extending in a second direction over the first plurality of semiconductor bodies, the first gate structure having a first gate dielectric structure and a first gate electrode on the first gate dielectric structure, wherein each semiconductor body of the first plurality of semiconductor bodies has a first midpoint thickness; and a second semiconductor device having a second plurality of semiconductor bodies extending in the first direction between a second source region and a second drain region, and a second gate structure extending in the second direction over the second plurality of semiconductor bodies, the second gate structure having a second gate dielectric structure and a second gate electrode on the second gate dielectric structure, wherein each semiconductor body of the second plurality of semiconductor bodies has a second midpoint thickness that is at least 1 nm less than the first midpoint thickness; wherein the first gate dielectric structure includes a first gate oxide layer and the second gate dielectric structure includes a second gate oxide layer, wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the first plurality of semiconductor bodies comprises a plurality of first semiconductor nanoribbons and the second plurality of semiconductor bodies comprises a plurality of second semiconductor nanoribbons. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the first gate dielectric structure includes a first layer of high-k material and the second gate dielectric structure includes a second layer of high-k material. ### Claim 4 (depends on 3) The integrated circuit of claim 3, wherein the first layer of high-k material and the second layer of high-k material each have substantially the same thickness. ### Claim 5 (depends on 3) The integrated circuit of claim 3, wherein the first layer of high-k material and the second layer of high-k material each comprise hafnium and oxygen. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the first gate dielectric structure does not include a layer of high-k material and the second gate dielectric structure does include a layer of high-k material. ### Claim 7 (depends on 1) A printed circuit board comprising the integrated circuit of claim 1. ### Claim 8 An electronic device, comprising: a chip package comprising one or more dies, at least one of the one or more dies comprising a first semiconductor device having a first plurality of semiconductor nanoribbons extending in a first direction between a first source region and a first drain region, and a first gate structure extending in a second direction over the first plurality of semiconductor nanoribbons, the first gate structure having a first gate dielectric structure and a first gate electrode on the first gate dielectric structure, wherein each nanoribbon of the first plurality of semiconductor nanoribbons has a first midpoint thickness; and a second semiconductor device having a second plurality of semiconductor nanoribbons extending in the first direction between a second source region and a second drain region, and a second gate structure extending in the second direction over the second plurality of semiconductor nanoribbons, the second gate structure having a second gate dielectric structure and a second gate electrode on the second gate dielectric structure, wherein each nanoribbon of the second plurality of semiconductor nanoribbons has a second midpoint thickness that is at least 1 nm less than the first midpoint thickness; wherein the first gate dielectric structure includes a first gate oxide layer and the second gate dielectric structure includes a second gate oxide layer, wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer. ### Claim 9 (depends on 8) The electronic device of claim 8, wherein the first gate dielectric structure includes a first layer of high-k material and the second gate dielectric structure includes a second layer of high-k material. ### Claim 10 (depends on 9) The electronic device of claim 9, wherein the first layer of high-k material and the second layer of high-k material each comprise hafnium and oxygen. ### Claim 11 (depends on 8) The electronic device of claim 8, wherein the first gate dielectric structure does not include a layer of high-k material and the second gate dielectric structure does include a layer of high-k material. ### Claim 12 (depends on 8) The electronic device of claim 8, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board. ### Claim 13 An integrated circuit comprising: a first semiconductor device having a plurality of first semiconductor nanoribbons extending in a first direction between a first source region and a first drain region, and a first gate structure extending in a second direction over the plurality of first semiconductor nanoribbons, the first gate structure having a first gate dielectric structure and a first gate electrode on the first gate dielectric structure; and a second semiconductor device having a plurality of second semiconductor nanoribbons extending in the first direction between a second source region and a second drain region, and a second gate structure extending in the second direction over the plurality of second semiconductor nanoribbons, the second gate structure having a second gate dielectric structure and a second gate electrode on the second gate dielectric structure; wherein the first gate dielectric structure includes a first gate oxide layer and the second gate dielectric structure includes a second gate oxide layer, wherein the first gate oxide layer is thicker than the second gate oxide layer, and wherein each nanoribbon of the plurality of first semiconductor nanoribbons has a first midpoint thickness and each nanoribbon of the plurality of second semiconductor nanoribbons has a second midpoint thickness that is at least 1 nm less than the first midpoint thickness. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein the first gate dielectric structure includes a first layer of high-k material and the second gate dielectric structure includes a second layer of high-k material. ### Claim 15 (depends on 14) The integrated circuit of claim 14, wherein the first layer of high-k material and the second layer of high-k material each have substantially the same thickness. ### Claim 16 (depends on 14) The integrated circuit of claim 14, wherein the first layer of high-k material and the second layer of high-k material each comprise hafnium and oxygen. ### Claim 17 (depends on 13) The integrated circuit of claim 13, wherein the first gate dielectric structure does not include a layer of high-k material and the second gate dielectric structure does include a layer of high-k material. ### Claim 18 (depends on 13) The integrated circuit of claim 13, wherein the first midpoint thickness is in the range of 12 angstroms to 20 angstroms greater than the second midpoint thickness, and wherein the first gate oxide layer has a thickness between 3 nm and 5 nm. ### Claim 19 (depends on 1) The integrated circuit of claim 1, wherein the first gate oxide layer has a thickness between 3 nm and 5 nm. ### Claim 20 (depends on 8) The electronic device of claim 8, wherein the first gate oxide layer has a thickness between 3 nm and 5 nm.