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US 12,765,054 B2Granted
Semiconductor device and manufacturing method thereof
AssigneeNational Institute of Advanced Industrial Science and Technology
InventorsMitsuo Okamoto, Atsushi Yao, Hiroshi Sato, Shinsuke Harada
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Abstract
A semiconductor device includes, on an n-type semiconductor substrate, a power transistor, an n-type transistor, and a p-type transistor on a laminated semiconductor substrate that laminates an n-type drift layer, a p-type; the power transistor has a trench gate electrode penetrating through the base layer; the p-type transistor is formed in an n-type well region formed in the base layer, and the n-type transistor is formed in a p-type well region further formed in the base layer or n-type well region; and a p-type impurity concentration of the buried channel region of the p-type transistor is equal to a p-type impurity concentration of the base layer.
Claims15
A semiconductor device comprising:
- a semiconductor substrate having a first main surface and a second main surface opposing the first main surface;
- a first semiconductor layer of a first conductivity type, the first semiconductor layer being provided on the first main surface of the semiconductor substrate;
- a second semiconductor layer provided on the first semiconductor layer and having a first portion of the first conductivity type and a second portion of a second conductivity type;
- a third semiconductor layer of the second conductivity type, the third semiconductor layer being provided on the second semiconductor layer;
- a power transistor provided in a power transistor region that is a part of a plan view layout on the first main surface of the semiconductor substrate;
- and
- a drive circuit of the power transistor provided in a CMOS region that is another part of the plan view layout of the semiconductor substrate, the drive circuit being configured by a p-type MOSFET and an n-type MOSFET,
- wherein the power transistor has:
- a power source region of the first conductivity type, the power source region being selectively provided in a portion of the third semiconductor layer;
- a trench groove penetrating through the power source region and the third semiconductor layer and having a depth reaching the second semiconductor layer;
- a trench gate electrode provided in the trench groove via a trench gate insulating film;
- a first source electrode connected to the power source region;
- and
- a first drain electrode provided on the second main surface,
- wherein the p-type MOSFET has:
- a first source region of the second conductivity type and a first drain region of the second conductivity type, the first source region and the first drain region being formed in a first well region of the first conductivity type, the first well region being provided in a part of the third semiconductor layer;
- a buried channel region of the second conductivity type, the buried channel region being provided between the first source region and the first drain region;
- and
- a first gate electrode provided over the buried channel region via a first gate insulating film,
- wherein the n-type MOSFET has:
- a second source region of the first conductivity type and a second drain region of the first conductivity type, the second source region and the second drain region being provided in a part of the third semiconductor layer;
- a channel region provided between the second source region and the second drain region;
- and
- a second gate electrode provided on the channel region via a second gate insulating film, and
- wherein an impurity concentration of the second conductivity type of the buried channel region is equal to an impurity concentration of the second conductivity type of the third semiconductor layer.
22 more elements
A manufacturing method of a semiconductor device, the method comprising the steps of:
- (a) preparing a semiconductor substrate having a first main surface and a second main surface opposing the first main surface, the first main surface including a power transistor region and a CMOS region;
- (b) forming a first semiconductor layer of a first conductivity type on the first main surface of the semiconductor substrate by using an epitaxial growth method;
- (c) forming a second semiconductor layer on the first semiconductor layer by using the epitaxial growth method, and forming a first portion of the first conductivity type and a second portion of the second conductivity type in the second semiconductor layer by using an ion implantation method;
- (d) forming a third semiconductor layer of the second conductivity type on the second semiconductor layer by using the epitaxial growth method;
- (e) forming a well region of the first conductivity type in the CMOS region by using the ion implantation method;
- (f) forming a trench groove penetrating through the third semiconductor layer and having a depth reaching the second semiconductor layer in the power transistor region;
- and
- (g) forming a power transistor in the power transistor region by providing a power source region in the third semiconductor layer, a trench gate insulating film and a trench gate electrode in the trench groove, forming a p-type MOSFET in the CMOS region by providing a first source region, a buried channel region, and a first drain region in the well region, a first gate insulating film and a first gate electrode on the buried channel region, and forming an n-type MOSFET in the CMOS region by providing a second source region, a channel region, and a second drain electrode in the third semiconductor layer, a second gate insulating film and a second gate electrode on the channel region,
- wherein in the step (e), an impurity of the first conductivity type is ion-implanted at a position deeper than that of the buried channel region so as to leave the buried channel region of the second conductivity type, the buried channel region having a desired thickness on a surface of the third semiconductor layer.
6 more elements
Dependencies are inferred from the claim text.