Three dimensional integrated circuit and fabrication thereof
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung University
InventorsYi-Chun Liu, Chun-Yi Cheng, Chien-Te Tu, Chee-Wee Liu
Life of this patent
Estimating the term…
Abstract
A method includes following steps. A first transistor is formed on a substrate. A first dielectric layer is formed over the first transistor. A first trench is formed in the first dielectric layer. An amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. The amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. A second transistor is formed over the crystalline semiconductor layer.
Claims20
A method comprising:
- forming a first transistor on a substrate;
- forming a first dielectric layer over the first transistor;
- forming a first trench and a second trench in the first dielectric layer, wherein a bottom of the first trench and a bottom of the second trench are at the substrate, wherein the first transistor is laterally between the first trench and the second trench;
- depositing an amorphous semiconductor layer in the first trench and over the first dielectric layer, wherein the amorphous semiconductor layer is further deposited in the second trench;
- crystallizing the amorphous semiconductor layer into a crystalline semiconductor layer;
- and
- forming a second transistor over the crystalline semiconductor layer.
A method comprising:
- forming a first transistor on a substrate;
- forming a dielectric layer over the substrate;
- etching a first trench in the dielectric layer until the substrate is exposed in the first trench;
- forming an amorphous semiconductor material in the first trench and over the dielectric layer;
- performing an anneal process on the amorphous semiconductor material, the anneal process turning the amorphous semiconductor material into a crystalline semiconductor material;
- forming an epitaxial stack on the crystalline semiconductor material, the epitaxial stack comprising first semiconductor layers and second semiconductor layers alternating with the first semiconductor layers;
- and
- replacing the first semiconductor layers with a gate structure.
A method comprising:
- forming a first transistor over a substrate;
- forming a first dielectric layer over the first transistor;
- forming a first crystalline semiconductor plug extending through the first dielectric layer;
- forming a crystalline semiconductor lateral portion extending along a top surface of the first dielectric layer, wherein the crystalline semiconductor lateral portion is formed of a same material as the first crystalline semiconductor plug;
- and
- forming a second transistor over the crystalline semiconductor lateral portion, wherein the first crystalline semiconductor plug is spaced apart from the crystalline semiconductor lateral portion.
Dependencies are inferred from the claim text.