# US 12,765,048 B2 · Semiconductor device structure and methods of forming the same

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- Number: US 12,765,048 B2
- Document ID: US12765048B2
- Status: Granted
- Kind: B2
- Application number: 18/488,251
- Filed: 2023-10-17
- Published: 2025-02-06
- Granted: 2026-10-13
- Earliest claimed: 2023-08-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Cheng-I Lin; Shu-Han Chen; Chi On Chui
- Web page: https://patentgrep.com/patent/US12765048B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device structure and methods of forming the same are described. The structure includes a first semiconductor layer disposed over a substrate, the first semiconductor layer has an edge portion and a center portion, and a height of the center portion is substantially greater than a height of the edge portion. The structure further includes a dielectric spacer disposed below and in contact with the edge portion of the first semiconductor layer, a gate dielectric layer surrounding the center portion of the first semiconductor layer, and a gate electrode layer disposed on the gate dielectric layer surrounding the center portion of the first semiconductor layer.

## Claims

### Claim 1

A method, comprising:
forming first and second fin structures, wherein the first fin structure comprises a first plurality of semiconductor layers, and the second fin structure comprises a second plurality of semiconductor layers;
forming a mask layer surrounding the second plurality of semiconductor layers, wherein the first plurality of semiconductor layer are exposed;
increasing dimensions of each semiconductor layer of the first plurality of semiconductor layers;
removing the mask layer;
depositing a gate dielectric layer surrounding the first and second pluralities of semiconductor layers;
forming a first gate electrode layer surrounding the second plurality of semiconductor layers; and
forming a second gate electrode layer surrounding the first plurality of semiconductor layers.

### Claim 2 (depends on 1)

The method of claim 1, further comprising increasing the dimensions of each semiconductor layer of the first plurality of semiconductor layers and dimensions of each semiconductor layer of the second plurality of semiconductor layers after removing the mask layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the mask layer comprises:
depositing a dielectric layer to surround each semiconductor layer of the first and second pluralities of semiconductor layers;
forming a photoresist over a portion of the dielectric layer surrounding the second plurality of semiconductor layers; and
removing a portion of the dielectric layer surrounding the first plurality of semiconductor layers.

### Claim 4 (depends on 3)

The method of claim 3, further comprising removing the photoresist after increasing the dimensions of each semiconductor layer of the first plurality of semiconductor layers.

### Claim 5 (depends on 1)

The method of claim 1, wherein the dimensions of each semiconductor layer of the first plurality of semiconductor layers are increased by an epitaxial deposition process.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first and second gate electrode layers are formed on the gate dielectric layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first gate electrode layer interfaces the second gate electrode layer.

### Claim 8

A method, comprising:
forming first and second fin structures, wherein the first fin structure comprises a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer, and the second fin structure comprises a third semiconductor layer and a fourth semiconductor layer disposed over the third semiconductor layer;
increasing dimensions of the first and second semiconductor layers without increasing dimensions of the third and fourth semiconductor layers;
depositing a gate dielectric layer surrounding the first, second, third, and fourth semiconductor layers;
forming a first gate electrode layer surrounding the first and second semiconductor layers; and
forming a second gate electrode layer surrounding the third and fourth semiconductor layers.

### Claim 9 (depends on 8)

The method of claim 8, wherein the dimensions of the first and second semiconductor layers are increased by a same amount.

### Claim 10 (depends on 8)

The method of claim 8, wherein the dimensions of the first and second semiconductor layers are increased by different amounts.

### Claim 11 (depends on 10)

The method of claim 10, wherein a width of the second semiconductor layer is greater than a width of the first semiconductor layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein a height of the second semiconductor layer is greater than a height of the first semiconductor layer.

### Claim 13 (depends on 8)

The method of claim 8, wherein the dimensions of the first and second semiconductor layers are increased by an epitaxy process.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming a mask layer on the third and fourth semiconductor layers prior to performing the epitaxy process.

### Claim 15 (depends on 14)

The method of claim 14, wherein the mask layer is formed by a conformal process.

### Claim 16

A method, comprising:
forming first and second fin structures, wherein the first fin structure comprises alternating first and second semiconductor layers, and the second fin structure comprises alternating third and fourth semiconductor layers;
removing the second and fourth semiconductor layers to expose the first and third semiconductor layers;
increasing dimensions of the first semiconductor layer without increasing dimensions of the third semiconductor layer;
depositing a gate dielectric layer surrounding the first and third semiconductor layers;
forming a first gate electrode layer surrounding the first semiconductor layer; and
forming a second gate electrode layer surrounding the third semiconductor layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising depositing a sacrificial gate structure around the first and second fin structures.

### Claim 18 (depends on 17)

The method of claim 17, further comprising removing the sacrificial gate structure to expose the first, second, third, and fourth semiconductor layers.

### Claim 19 (depends on 16)

The method of claim 16, further comprising depositing a mask layer around the first and third semiconductor layers.

### Claim 20 (depends on 19)

The method of claim 19, further comprising removing a portion of the mask layer to expose the first semiconductor layer.