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US 12,765,047 B2Granted
Field effect transistor and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Ruei Jhan, Kuan-Ting Pan, Shi-Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang
Life of this patent
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Abstract
A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, an isolation feature embedded in the substrate and laterally between the first and second semiconductor channels, a first liner layer laterally surrounding the isolation feature between the isolation feature and the first semiconductor channel, and a second liner layer laterally surrounding the first liner layer between the first liner layer and the first semiconductor channel.
Claims20
A device, comprising:
- a substrate;
- a first semiconductor fin protruding from the substrate and having a pair of first sidewalls opposite each other in a first lateral direction and a pair of second sidewalls opposite each other in a second lateral direction;
- a second semiconductor fin protruding from the substrate and laterally offset from the first semiconductor fin;
- a first semiconductor layer on the first sidewalls of the first semiconductor fin and on a top surface of the substrate between the first and second semiconductor fins;
- a second semiconductor layer on the first semiconductor layer and in contact with the second sidewalls of the first semiconductor fin and separated from first sidewalls of the first semiconductor fin by the first semiconductor layer;
- a first semiconductor channel over the first semiconductor fin;
- a second semiconductor channel over the second semiconductor fin and laterally offset from the first semiconductor channel;
- an isolation feature over the substrate and laterally between the first and second semiconductor fins, the isolation feature comprising an oxide material and having a top surface that is lower than a top surface of the first semiconductor fin, the isolation feature in contact with the second semiconductor layer and separated from the substrate and the first sidewalls of the first semiconductor fin by the first semiconductor layer and the second semiconductor layer;
- and
- a gate structure including a gate metal positioned between the top surface of the first semiconductor fin and a bottom surface of the first semiconductor channel.
7 more elements
A device comprising:
- a substrate;
- a first isolation region on the substrate;
- a second isolation region on the substrate and laterally offset from the first isolation region in a first direction;
- a first semiconductor fin protruding from the substrate between the first and second isolation regions, the first and second isolation regions each having a top surface that is lower than a top surface of the first semiconductor fin, on a side of the semiconductor fin;
- a first inactive fin structure on the first isolation region;
- a second inactive fin structure on the second isolation region;
- a first gate all around transistor including a channel above the first semiconductor fin and laterally between the first isolation region and the second isolation region;
- a first semiconductor layer in contact with a first pair of opposing sidewalls of the first semiconductor fin and a top surface of the substrate below the first and second isolation structures;
- and
- a second semiconductor layer in contact with the first semiconductor layer and the first isolation region, wherein the second semiconductor layer is in contact with a pair of second opposing sides of the first semiconductor fin.
7 more elements
A device, comprising:
- a first fin stack including a first nanostructure, and a first sidewall;
- a second fin stack including a second nanostructure, wherein the first sidewall is facing the second fin stack;
- a first liner layer in contact with two opposing sides of the first fin stack;
- and
- a second liner layer on the first liner layer, the second liner layer including a first recess between the first fin stack and the second fin stack, wherein the second liner layer is in contact with two different opposing sides of the first fin stack;
- and
- an isolation region in the first recess,
- wherein the isolation region comprises silicon oxide, and the first and second liner layers each comprise a semiconductor material, wherein the semiconductor material is silicon germanium.
5 more elements
Dependencies are inferred from the claim text.