Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate including an active pattern;
• a channel pattern and a source/drain pattern that are on the active pattern and connected to each other;
• an active contact coupled to the source/drain pattern;
• and
• a metal layer on the active contact,
• an interconnection line in the metal layer that is electrically connected to the active contact through a via,
• wherein the active contact comprises a first barrier metal, a first filler metal on the first barrier metal, and an upper insulating pattern on the first filler metal and the first barrier metal,
• wherein the upper insulating pattern is in contact with upper surfaces of the first filler metal and the first barrier metal,
• wherein an upper surface of the upper insulating pattern is coplanar with an upper surface of a gate contact,
• wherein a top surface of a first insulating pattern is coplanar with an upper surface of a gate capping pattern, a second insulating pattern on the first insulating pattern cover the gate capping pattern and a top surface of a second insulating pattern is coplanar with the upper surface of the gate contact,
• wherein the via comprises a second barrier metal and a second filler metal on the second barrier metal,
• wherein each of the first and second barrier metals comprises a metal nitride layer,
• wherein each of the first and second filler metals comprises at least one of molybdenum, tungsten, ruthenium, cobalt, or vanadium, wherein the first filler metal comprises a first crystalline region having a body-centered cubic (BCC) structure and the second filler metal comprises a second crystalline region having the body-centered cubic (BCC) structure;
• and
• wherein a proportion of the body-centered cubic (BCC) structure in the first filler metal is higher than a proportion of a body-centered cubic (BCC) structure in the second filler metal.

A semiconductor device, comprising:

• a substrate including a PMOSFET region and an NMOSFET region;
• a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region;
• a first channel pattern and a first source/drain pattern on the first active pattern;
• a second channel pattern and a second source/drain pattern on the second active pattern;
• a gate electrode on the first and second channel patterns;
• a gate insulating layer between the gate electrode and the first and second channel patterns;
• a gate spacer on a side surface of the gate electrode;
• a gate capping pattern on a top surface of the gate electrode;
• a gate cutting pattern penetrating the gate electrode;
• an interlayer insulating layer on the gate capping pattern and the gate cutting pattern;
• active contacts that penetrates the interlayer insulating layer and is electrically connected to the first and second source/drain patterns;
• metal-semiconductor compound layers between the active contact contacts and the first and second source/drain patterns, respectively;
• a gate contact that penetrates the interlayer insulating layer and the gate capping pattern and is electrically connected to the gate electrode;
• a first metal layer on the interlayer insulating layer, the first metal layer comprising a power line, which overlaps the gate cutting pattern in a direction normal to a surface of the substrate, and
• first interconnection lines, which are electrically connected to the active and gate contacts, respectively;
• and
• a second metal layer on the first metal layer,
• wherein the first source/drain pattern comprises a buffer layer on the substrate and a main layer on the buffer layer,
• wherein the second metal layer comprises second interconnection lines electrically connected to the first metal layer,
• wherein a first active contact of the active contacts comprises a first barrier metal, a first filler metal on the first barrier metal, and an upper insulating pattern on the first filler metal and the first barrier metal,
• wherein the upper insulating pattern is in contact with upper surfaces of the first filler metal and the first barrier metal,
• wherein an upper surface of the upper insulating pattern is coplanar with an upper surface of the gate contact,
• wherein a top surface of a first insulating pattern is coplanar with an upper surface of a gate capping pattern, a second insulating pattern on the first insulating pattern cover the gate capping pattern and a top surface of a second insulating pattern is coplanar with the upper surface of the gate contact,
• wherein the gate contact comprises a second barrier metal and a second filler metal on the second barrier metal, and
• a proportion of a body-centered cubic (BCC) structure in the first filler metal is higher than a proportion of a body-centered cubic (BCC) structure in the second filler metal.