Field effect transistor with narrowed spacer and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang
Life of this patent
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Abstract
A device includes: a stack of semiconductor channels; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; a source/drain contact on the source/drain region; and a gate spacer between the source/drain contact and the gate structure. The gate spacer includes: a first spacer layer in contact with the gate structure; and a second spacer layer between the first spacer layer and the source/drain contact, the second spacer layer having a first portion on the stack and a second portion on the first portion, the second portion being thinner than the first portion.
Claims20
A method, comprising:
- forming a sacrificial gate structure over a stack of nanostructures over a substrate;
- forming a gate spacer on a sidewall of the sacrificial gate structure;
- forming a source/drain opening by recessing the stack;
- forming inner spacer recesses in the stack;
- forming an inner spacer layer on the gate spacer and in the inner spacer recesses;
- trimming a first upper portion of the inner spacer layer;
- increasing width of the source/drain opening by trimming a second upper portion of the gate spacer while removing excess portions of the inner spacer layer outside the inner spacer recesses;
- and
- forming a source/drain region in the source/drain opening after the increasing width.
A method, comprising:
- forming a sacrificial gate structure over a stack of nanostructures over a substrate;
- forming a gate spacer on a sidewall of the sacrificial gate structure;
- after forming the gate spacer, forming a source/drain opening by recessing the stack;
- increasing width of the source/drain opening by trimming an upper portion of the gate spacer;
- and
- forming a source/drain region in the source/drain opening after the increasing width.
A method, comprising:
- forming a sacrificial gate structure over a stack of nanostructures over a substrate;
- forming a gate spacer on a sidewall of the sacrificial gate structure;
- forming a source/drain opening by recessing the stack;
- forming inner spacer recesses in the stack;
- forming a mask layer in the source/drain opening prior to forming an inner spacer layer;
- trimming an upper portion of the gate spacer while the mask layer is in the source/drain opening;
- removing the mask layer;
- forming the inner spacer layer in the inner spacer recesses after the removing the mask layer;
- and
- forming a source/drain region in the source/drain opening.
Dependencies are inferred from the claim text.