# US 12,765,028 B2 · Semiconductor structure and forming method therefor

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- Number: US 12,765,028 B2
- Document ID: US12765028B2
- Status: Granted
- Kind: B2
- Application number: 18/124,768
- Filed: 2023-03-22
- Published: 2023-07-27
- Granted: 2026-10-13
- Earliest claimed: 2020-09-25
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Bo Su; Hansu Oh
- Web page: https://patentgrep.com/patent/US12765028B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 50/283: {by chemical means}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and a forming method therefor are provided. The forming method includes: providing a base, a gate structure, a source/drain doped area, and a bottom dielectric layer; forming a source/drain interconnect layer running through the bottom dielectric layer on a top of the source/drain doped area; forming a top dielectric layer on the bottom dielectric layer; forming a gate contact running through the top dielectric layer on a top of the gate structure and a source/drain contact running through the top dielectric layer on a top of the source/drain interconnect layer; forming a sacrificial side wall layer on side walls of the gate contact and the source/drain contact; forming a gate plug filling the gate contact and a source/drain plug filling the source/drain contact; removing the sacrificial side wall layer to form a first gap; and forming a sealing layer sealing the first gap.

## Claims

### Claim 1

A semiconductor structure, comprising:
a base;
a gate structure located on the base;
a source/drain doped area located in the base on two sides of the gate structure;
a source/drain interconnect layer located on a top of the source/drain doped area and contacting the source/drain doped area;
a gate plug located on a top of the gate structure and contacting the gate structure;
a source/drain plug located on a top of the source/drain interconnect layer and contacting the source/drain interconnect layer;
a dielectric layer, covering side walls of the gate plug and the source/drain plug and filling between the gate plug and the source/drain plug;
a first gap located between the side wall of the gate plug and the dielectric layer and between the side wall of the source/drain plug and the dielectric layer, wherein the first gap being is laterally bounded by the dielectric layer, and the first gap located between the side wall of the source/drain plug and the dielectric layer is isolated from the gate structure by the dielectric layer; and
a sealing layer located on the dielectric layer and sealing the first gap, a first portion of the first gap located on the side wall of the source/drain plug or a second portion of the first gap located on the side wall of the gate plug and the sealing layer forming a first air gap.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein the base comprises an active area, and the semiconductor structure further comprises:
a gate cap layer located between the top of the gate structure and the dielectric layer; and
a source/drain cap layer located between the top of the source/drain interconnect layer and the dielectric layer, wherein the gate plug is located above the gate structure in the active area.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein a width of the first gap is 10 Å to 40 Å along a direction perpendicular to the side wall of the gate plug or the source/drain plug.

### Claim 4 (depends on 1)

The semiconductor structure according to claim 1, wherein the semiconductor structure further comprises:
a contact etch stop layer located on the base between the side wall of the source/drain interconnect layer and the gate structure and arranged opposite to the side wall of the gate structure, wherein a second gap is formed between the contact etch stop layer and the side wall of the gate structure; and
the dielectric layer fills the second gap, or the dielectric layer seals a top of the second gap, and the second gap and the dielectric layer form a second air gap.

### Claim 5 (depends on 1)

The semiconductor structure according to claim 1, wherein a material of the dielectric layer comprises a low k dielectric material or an ultra-low k dielectric material.