Semiconductor device having vertically stacked channels connected to a multi-layer source/drain pattern with an active contact recessed therein

A semiconductor device, comprising:

• a substrate including an active region;
• a source/drain pattern on the active region, the source/drain pattern including a first inner surface, the source/drain pattern being among a plurality of source/drain patterns;
• channel patterns on the active region and connected to the plurality of source/drain patterns, each of the channel patterns including a plurality of semiconductor patterns, the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the plurality of semiconductor patterns being a first semiconductor pattern;
• gate electrodes on the channel patterns, respectively;
• an active contact electrically connected to the source/drain pattern;
• and
• an intermediate layer on the first inner surface, wherein
• the active contact is on the intermediate layer,
• the source/drain pattern includes a first layer connected to the plurality of semiconductor patterns and a second layer interposed between the first layer and the active contact,
• a level of a topmost surface of the second layer is lower than a level of a bottommost surface of the active contact, and
• a level of a bottom surface of the first inner surface is lower than a top surface of the first semiconductor pattern.

A semiconductor device, comprising:

• a substrate including an active region;
• a device isolation layer on the active region, the device isolation layer defining an active pattern on the active region;
• a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, a lowermost one of the plurality of semiconductor patterns being a first semiconductor pattern;
• a source/drain pattern on the active pattern;
• a gate electrode on the plurality of semiconductor patterns, the gate electrode including a portion interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns;
• a gate insulating layer between the adjacent semiconductor patterns and the portion of the gate electrode;
• an inner spacer between the gate insulating layer and the source/drain pattern;
• a gate spacer on a side surface of the gate electrode;
• a gate capping pattern on a top surface of the gate electrode;
• an interlayer insulating layer on the gate capping pattern;
• an active contact penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern;
• a metal layer between the active contact and the source/drain pattern;
• a gate contact penetrating the interlayer insulating layer and the gate capping pattern, the gate contact being electrically connected to the gate electrode;
• a first metal layer on the interlayer insulating layer, the first metal layer including a power line and a first interconnection line, the power line and the first interconnection line being electrically connected to the active contact and gate contact;
• and
• a second metal layer on the first metal layer,
• the second metal layer includes second interconnection lines electrically connected to the first metal layer,
• the source/drain pattern include a first layer connected to the plurality of semiconductor patterns and a second layer interposed between the first layer and the active contact,
• a level of a topmost surface of the second layer is lower than a level of a bottommost surface of the active contact, and
• a level of a lowermost portion of the active contact is lower than a level of a top surface of the first semiconductor pattern.