# US 12,765,016 B2 · Semiconductor device with source/drain including stressor elements and method for manufacturing the same

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- Number: US 12,765,016 B2
- Document ID: US12765016B2
- Status: Granted
- Kind: B2
- Application number: 18/154,275
- Filed: 2023-01-13
- Published: 2024-04-11
- Granted: 2026-10-13
- Earliest claimed: 2022-10-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ding-Kang Shih
- Web page: https://patentgrep.com/patent/US12765016B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a channel structure including a plurality of channel features which are spaced apart from each other, and which include first semiconductor elements, and two source/drain features disposed at two opposite sides of the channel structure such that each of the channel features interconnects the source/drain features. A major portion of each of the source/drain features includes second semiconductor elements, stressor elements which have an atomic radius different from that of the second semiconductor elements, and which are present in an amount sufficient to permit the source/drain features to apply a first stress to the channel features, and a certain degree of lattice defects present such that the source/drain features including the stressor elements apply a second stress to the channel features. The second stress is opposite to the first stress. A method for manufacturing the semiconductor device is also disclosed.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
forming a channel structure; and
forming two source/drain features at two opposite sides of the channel structure, the two source/drain features having an n-type conductivity, a major portion of each of the two source/drain features including silicon elements and stressor elements, the stressor elements having an atomic radius greater than an atomic radius of the silicon elements,
wherein the two source/drain features are formed in a growth condition to introduce a certain degree of lattice defects in the major portion such that the major portion including the stressor elements applies a tensile stress to the channel structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the channel structure includes channel features which are made of a semiconductor material;
first ends of the channel features interface one of the two source/drain features and are spaced apart from each other by first inner spacers;
second ends of the channel features interface the other one of the two source/drain features and are spaced apart from each other by second inner spacers; and
each of the first inner spacers and the second inner spacers is made of a dielectric material, such that during formation of the two source/drain features, each of which covers the semiconductor material of the channel features and the dielectric material of corresponding ones of the first inner spacers and the second inner spacers, the lattice defects are introduced into the two source/drain features.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a gate feature disposed to surround the channel features; and
forming a gate dielectric layer disposed to separate the gate feature from the channel features and the first inner spacers and the second inner spacers.

### Claim 4 (depends on 1)

The method of claim 1, wherein each of the two source/drain features further includes a capping portion which is formed on the major portion, and which has an electrical resistance lower than an electrical resistance of the major portion.

### Claim 5

A method for manufacturing a semiconductor device, comprising:
forming two recesses at two opposite sides of a stack, the stack including channel features and sacrificial features which are disposed to alternate with the channel features, the channel features and the sacrificial features being made of different materials, the channel features including first semiconductor elements;
recessing the sacrificial features to form grooves;
forming inner spacers respectively in the grooves such that the inner spacers are disposed between corresponding adjacent ones of the channel features; and
growing two source/drain features respectively in the two recesses, each of the two source/drain features having a p-type conductivity and including a major portion, the major portion being formed by growing epitaxial regions on the channel features, growing amorphous regions on the inner spacers, and growing a central region to fill a respective one of the two recesses, the major portion including
second semiconductor elements,
p-type dopants,
stressor elements which are different from the p-type dopants and which have an atomic radius less than an atomic radius of the second semiconductor elements, and
a certain degree of dislocations which propagate from the amorphous regions into the epitaxial regions or the central region of the major portion such that the major portion including the stressor elements applies a compressive stress to the channel features; and
after growing the two source/drain features, removing the sacrificial features.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first semiconductor elements and the second semiconductor elements are silicon elements.

### Claim 7 (depends on 5)

The method of claim 5, wherein
each of the channel features has a first end and a second end which respectively interface the two source/drain features,
the first end of each of the channel features interfaces the major portion of one of the two source/drain features, and
the second end of each of the channel features interfaces the major portion of the other one of the two source/drain features.

### Claim 8 (depends on 5)

The method of claim 5, wherein
each of the two source/drain features further includes a capping portion disposed on the major portion, an electrical resistance of the capping portion being lower than an electrical resistance of the major portion,
the capping portion includes silicon elements and segregation elements,
an atomic concentration of the segregation elements in the capping portion is greater than an atomic concentration of a dopant in a central region of the major portion, and
the segregation elements include boron, germanium, gallium, or combinations thereof.

### Claim 9 (depends on 5)

The method of claim 5, wherein the stressor elements include carbon.

### Claim 10

A method for manufacturing a semiconductor device, comprising:
forming a recess in a base portion and at a side of a stack, the stack being disposed on the base portion and including channel features and sacrificial features which are disposed to alternate with the channel features, the channel features and the sacrificial features being made of different materials, the channel features including first semiconductor elements and having a {110} crystal plane facing the recess;
growing a semiconductor layer on a bottom of the recess by a bottom-up epitaxial growth, where the semiconductor layer has a growth rate over a {100} crystal plane of the base portion higher than a growth rate over the {110} crystal plane of the channel features;
depositing a dielectric layer on the semiconductor layer; and
growing a source/drain portion on the dielectric layer and in the recess, the source/drain portion having an n-type conductivity and including
silicon elements,
n-type dopants,
stressor elements which are different from the n-type dopants and having an atomic radius greater than an atomic radius of the silicon elements, and
a certain degree of dislocations present such that the source/drain portion including the stressor elements applies a tensile stress to the channel features.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a metal silicide layer over the source/drain portion; and
introducing segregation elements between the metal silicide layer and the source/drain portion.

### Claim 12 (depends on 11)

The method of claim 11, wherein the segregation elements include phosphorous, arsenic, antimony, or combinations thereof.

### Claim 13 (depends on 1)

The method of claim 1, wherein the stressor elements include germanium, tin, or a combination thereof.

### Claim 14 (depends on 13)

The method of claim 13, wherein the stressor elements are present in an atomic concentration ranging from 10% to 80% based on total atoms of the silicon elements and the stressor elements.

### Claim 15 (depends on 1)

The method of claim 1, wherein the stressor elements serve as n-type dopants, and include antimony, bismuth, or a combination thereof, an atomic concentration of the stressor elements in the major portion ranging from 1E19 atoms/cm3 to 1E21 atoms/cm3.

### Claim 16 (depends on 9)

The method of claim 9, wherein an atomic concentration of the stressor elements in the major portion is one to two orders of magnitude lower than an atomic concentration of the second semiconductor elements in the major portion.

### Claim 17 (depends on 9)

The method of claim 9, wherein the p-type dopants include boron.

### Claim 18 (depends on 10)

The method of claim 10, wherein the n-type dopants include phosphorous, arsenic, antimony, bismuth, or combinations thereof.

### Claim 19 (depends on 18)

The method of claim 18, wherein the stressor elements include germanium, tin, antimony, bismuth, or combinations thereof.

### Claim 20 (depends on 10)

The method of claim 10, wherein an atomic concentration of the stressor elements in the source/drain portion is greater than an atomic concentration of the n-type dopants in the source/drain portion.