Integrated circuit devices

An integrated circuit device comprising:

• a plurality of fin-type active areas extending in a first horizontal direction on a substrate;
• a plurality of nanosheets having surfaces that face fin top surfaces of the plurality of fin-type active areas, each of the plurality of nanosheets spaced apart from the fin top surfaces at different distances in a vertical direction;
• a plurality of gate lines extending in length on the plurality of fin-type active areas in a second horizontal direction that crosses the first horizontal direction, each of the plurality of gate lines surrounding the plurality of nanosheets;
• and
• a plurality of source/drain regions having side surfaces that face the plurality of nanosheets in the first horizontal direction,
• wherein the plurality of source/drain regions respectively have bottom surfaces in contact with the plurality of fin-type active areas,
• wherein each of the plurality of source/drain regions includes a respective plurality of semiconductor layers and at least one air gap located therein, wherein the at least one air gap includes an air gap located inside each of the plurality of semiconductor layers,
• and wherein each respective plurality of semiconductor layers includes:
• a first semiconductor layer in contact some of the plurality of nanosheets in contact with at least one of the plurality of fin-type active areas;
• a second semiconductor layer on the first semiconductor layer;
• and
• a third semiconductor layer on the second semiconductor layer.

An integrated circuit device comprising:

• a first fin-type active area extending in a first horizontal direction on a substrate and in a first region of the substrate;
• a second fin-type active area extending in the first horizontal direction on the substrate and in a second region of the substrate;
• a pair of first nanosheet stacks each including a plurality of first nanosheets having surfaces that face a first fin top surface of the first fin-type active area and spaced apart from the first fin top surface at different distances in a vertical direction;
• a pair of second nanosheet stacks each including a plurality of second nanosheets having surfaces that face a second fin top surface of the second fin-type active area and spaced apart from the second fin top surface at different distances in the vertical direction;
• a pair of first gate lines on the pair of first nanosheet stacks on the first in the first region, extending in length in a second horizontal direction that crosses the first horizontal direction, the pair of first gate lines spaced apart from each other in the first horizontal direction with a first distance therebetween
• a pair of second gate lines on the pair of second nanosheet stacks on the second fin-type active area in the second region, extending in length in the second horizontal direction and spaced apart from each other in the first horizontal direction with a second distance that is greater than the first distance therebetween;
• a first source/drain region in contact with the plurality of first nanosheets between the pair of first nanosheet stacks in the first region and on the first fin-type active area;
• and
• a second source/drain region in contact with the plurality of second nanosheets between the pair of second nanosheet stacks in the second region and on the second fin-type active area,
• wherein the first source/drain region has a bottom surface in contact with the first fin-type active area,
• wherein the first source/drain region includes a plurality of semiconductor layers and at least one air gap located therein,
• wherein the plurality of semiconductor layers include:
• a first semiconductor layer including a part in contact with each of the pair of first nanosheets and a part in contact with the first fin-type active area;
• a second semiconductor layer on the first semiconductor layer;
• and
• a third semiconductor layer on the second semiconductor layer,
• wherein each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes a Si1-xGex layer doped with boron (where, x≠0),
• wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer have different Ge content ratios,
• wherein the first source/drain region has a top surface at a higher vertical level than a vertical level of a top surface of a nanosheet having a greatest vertical distance from the first fin top surface among the plurality of first nanosheets, and
• wherein the second source/drain region has a top surface at a lower vertical level than a vertical level of the top surface of the first source/drain region, and
• wherein the second source/drain region does not include an air gap therein.