Semiconductor device that includes a multi-bridge channel field effect transistor

A semiconductor device comprising:

• a lower interlayer insulating layer;
• first and second active patterns extended in a first horizontal direction on the lower interlayer insulating layer, wherein the second active pattern is spaced apart from the first active pattern in a second horizontal direction that is different from the first horizontal direction;
• first to fourth gate electrodes extended in the second horizontal direction on the first and second active patterns, wherein the first to fourth gate electrodes are sequentially spaced apart from one another in the first horizontal direction;
• a gate cut extended in the first horizontal direction between the first active pattern and the second active pattern, wherein the gate cut separates each of the first to fourth gate electrodes in the second horizontal direction;
• a first source region disposed on the first active pattern and between the first gate electrode and the second gate electrode;
• a second source region disposed on the first active pattern and between the second gate electrode and the third gate electrode;
• a first drain region disposed on the first active pattern and between the third gate electrode and the fourth gate electrode;
• a third source region disposed on the second active pattern and between the first gate electrode and the second gate electrode;
• a second drain region disposed on the second active pattern and between the second gate electrode and the third gate electrode;
• a fourth source region disposed on the second active pattern and between the third gate electrode and the fourth gate electrode;
• a first contact extended in the second horizontal direction between the first gate electrode and the second gate electrode, wherein the first contact is connected to each of the first and third source regions;
• a second contact extended in the second horizontal direction between the second gate electrode and the third gate electrode, wherein the second contact is connected to the second source region;
• a third contact extended in the second horizontal direction between the third gate electrode and the fourth gate electrode, wherein the third contact is connected to the first drain region;
• a fourth contact extended in the second horizontal direction between the second gate electrode and the third gate electrode, wherein the fourth contact is spaced apart from the second contact in the second horizontal direction, and the fourth contact is connected to the second drain region;
• a fifth contact extended in the second horizontal direction between the third gate electrode and the fourth gate electrode, wherein the fifth contact is spaced apart from the third contact in the second horizontal direction, and the fifth contact is connected to the fourth source region;
• a lower wiring layer disposed inside the lower interlayer insulating layer, wherein the lower wiring layer is extended in the first horizontal direction below the gate cut;
• and
• a through via crossing the gate cut, wherein the through via connects the lower wiring layer with the first contact,
• wherein each of the second contact and the fourth contact is electrically insulated from the lower wiring layer between the second gate electrode and the third gate electrode, and
• wherein each of the third contact and the fifth contact is electrically insulated from the lower wiring layer between the third gate electrode and the fourth gate electrode.

A semiconductor device comprising:

• a lower interlayer insulating layer;
• first and second active patterns extended in a first horizontal direction on the lower interlayer insulating layer, the second active pattern spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction;
• a first plurality of nanosheets stacked to be spaced apart from each other in a vertical direction on the first active pattern;
• a second plurality of nanosheets stacked to be spaced apart from each other in the vertical direction on the second active pattern;
• a gate electrode extended in the second horizontal direction, which is different from the first horizontal direction, on the first and second active patterns, wherein the gate electrode at least partially surrounds the first and second plurality of nanosheets;
• a gate cut extended in the first horizontal direction between the first active pattern and the second active pattern, wherein the gate cut separates the gate electrode in the second horizontal direction;
• a first source region disposed on a first side of the gate electrode on the first active pattern;
• a second source region disposed on a second side of the gate electrode, which opposes the first side of the gate electrode in the first horizontal direction, on the first active pattern;
• a third source region disposed on the first side of the gate electrode on the second active pattern;
• a drain region disposed on the second side of the gate electrode on the second active pattern;
• a first contact extended on the first side of the gate electrode in the second horizontal direction, wherein the first contact is connected to each of the first and third source regions;
• a second contact extended on the second side of the gate electrode in the second horizontal direction, wherein the second contact is connected to the second source region;
• a third contact extended on the second side of the gate electrode in the second horizontal direction, wherein the third contact is spaced apart from the second contact in the second horizontal direction, and is connected to the drain region;
• a lower wiring layer disposed inside the lower interlayer insulating layer, wherein the lower wiring layer extends in the first horizontal direction between the first active pattern and the second active pattern, wherein at least a portion of the lower wiring layer protrudes from an upper surface of the lower interlayer insulating layer in the vertical direction below the first contact, wherein the lower wiring layer overlaps each of the first and second active patterns in the vertical direction;
• a through via disposed between the first source region and the third source region, wherein the through via is integrally formed with the first contact, wherein the through via crosses the gate cut, and connects the lower wiring layer with the first contact;
• a lower insulating layer disposed between the upper surface of the lower interlayer insulating layer and a lower surface of each of the first and second active patterns, the lower insulating layer being in contact with the lower wiring layer;
• and
• a field insulating layer disposed on the upper surface of the lower interlayer insulating layer, wherein the field insulating layer at least partially surrounds each of sidewalls of the lower insulating layer, sidewalls of the first active pattern and sidewalls of the second active pattern,
• wherein each of the second contact and the third contact is electrically insulated from the lower wiring layer between the second source region and the drain region, and
• wherein an upper surface of the lower insulating layer is formed to be higher than an upper surface of the lower wiring layer between the first source region and the third source region.