Semiconductor device with trench-typed power transistors and fabrication method thereof

A semiconductor device, comprising:

• a substrate, having a first conductivity type;
• a well region, having the first conductivity type and disposed in the substrate;
• a trench, disposed in the substrate and directly above the well region;
• a first trench gate and a second trench gate, disposed in the trench and laterally separated from each other;
• a dielectric isolation portion, disposed in the trench and between the first trench gate and the second trench gate;
• and
• a first doped region and a second doped region, having the first conductivity type, disposed in the substrate and laterally separated from each other, wherein the first doped region and the second doped region are located on two sides of the well region, respectively, a doping concentration of the well region is higher than respective doping concentrations of the first doped region and the second doped region, and a bottom surface of the well region, a bottom surface of the first doped region, and a bottom surface of the second doped region are substantially on the same plane.

A method of fabricating a semiconductor device, comprising:

• providing a substrate having a first conductivity type;
• forming a trench in the substrate;
• conformally forming a dielectric liner on sidewalls and a bottom surface of the trench;
• forming a first trench gate and a second trench gate in the trench and laterally separated from each other to expose a portion of the dielectric liner on the bottom surface of the trench and between the first trench gate and the second trench gate;
• forming a well region in the substrate, wherein the well region is located directly below a region between the first trench gate and the second trench gate;
• performing a thermal oxidation process to form an oxide layer in the trench and between the first trench gate and the second trench gate, wherein the oxide layer protrudes downward into the well region;
• and
• filling up the trench with a dielectric material layer, wherein the dielectric material layer and the oxide layer constitute a dielectric isolation portion, the dielectric isolation portion is located between the first trench gate and the second trench gate, and a middle region of a bottom surface of the dielectric isolation portion protrudes downward and is lower than two side regions of the bottom surface of the dielectric isolation portion.