Semiconductor structure with device including at least one in-well porous region
AssigneeGlobalFoundries U.S. Inc.
InventorsShesh Mani Pandey, Kaustubh Shanbhag, Rajendran Krishnasamy, Judson R. Holt
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AssigneeGlobalFoundries U.S. Inc.
InventorsShesh Mani Pandey, Kaustubh Shanbhag, Rajendran Krishnasamy, Judson R. Holt
Estimating the term…
Disclosed are embodiments of a structure including a semiconductor layer and a device, which has a well region within the semiconductor layer and at least one porous region within and shallower in depth than the well region. In some embodiments, the device can be a field effect transistor (FET) (e.g., a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFETs)) with a drain drift region that extends through the well region around the porous region(s) to a drain region. The porous region(s) can modify the electric field in this drain drift region, thereby improving device performance. Embodiments can vary with regard to the number, size, shape, configuration, etc. of the porous region(s) within the well region. Also disclosed herein are method embodiments for forming the semiconductor structure.
A structure comprising:
A structure comprising:
A method comprising:
Dependencies are inferred from the claim text.