# US 12,764,994 B2 · Fin field effect transistor (FinFET) device and method for forming the same

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- Number: US 12,764,994 B2
- Document ID: US12764994B2
- Status: Granted
- Kind: B2
- Application number: 18/338,759
- Filed: 2023-06-21
- Published: 2023-11-02
- Granted: 2026-10-13
- Earliest claimed: 2014-10-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Zhe-Hao Zhang; Tung-Wen Cheng; Che-Cheng Chang; Yung-Jung Chang; Chang-Yin Chen
- Web page: https://patentgrep.com/patent/US12764994B2

## CPC

- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.

## Claims

### Claim 1

A fin field effect transistor (FinFET) device structure, comprising:
a fin structure over a substrate; and
an epitaxial structure formed on a surface of the fin structure, wherein a surface of the epitaxial structure is substantially flat and extends from a first interface with a dielectric material to a second interface with the dielectric material opposite the first interface, wherein a horizontal line passes through an interface point of the surface of the fin structure and the epitaxial structure, and wherein the horizontal line intersects a direction parallel to the surface of the epitaxial structure at an angle of 90° to 175°, wherein the angle opens towards an interior of the epitaxial structure.

### Claim 2 (depends on 1)

The FinFET device structure of claim 1, wherein the surface of the epitaxial structure continuously extends along a crystallographic orientation.

### Claim 3 (depends on 2)

The FinFET device structure of claim 2, wherein the crystallographic orientation is (111).

### Claim 4 (depends on 1)

The FinFET device structure of claim 1, wherein a line extending in the direction parallel to the surface of the epitaxial structure contacts the surface of the fin structure.

### Claim 5 (depends on 1)

The FinFET device structure of claim 1, wherein the FinFET device structure is an NMOS device.

### Claim 6 (depends on 5)

The FinFET device structure of claim 5, wherein the epitaxial structure includes epitaxially grown silicon.

### Claim 7 (depends on 5)

The FinFET device structure of claim 5, wherein the epitaxial structure is doped with phosphorus to form a Si:P epitaxial structure.

### Claim 8

A fin field effect transistor (FinFET) device structure, comprising:
a semiconductor substrate;
a fin structure over the semiconductor substrate;
an epitaxial structure overlying a first surface of the fin structure, wherein a second surface of the epitaxial structure is substantially flat, wherein a first angle θ1 between a first line and the second surface is between 90° and 175°, the first angle extending through the epitaxial structure, and wherein the first line extends between a first point where the first surface intersects a first sidewall of the fin structure to a second point where the first surface intersects a second sidewall of the fin structure, the first sidewall opposite the second sidewall; and
a dielectric material extending to interface with both the fin structure and the epitaxial structure.

### Claim 9 (depends on 8)

The FinFET device structure of claim 8, wherein the second surface continuously extends along a first crystallographic orientation.

### Claim 10 (depends on 8)

The FinFET device structure of claim 8, wherein the second surface continuously extends along a [111] crystallographic orientation.

### Claim 11 (depends on 8)

The FinFET device structure of claim 8, wherein the first surface intersects the second surface.

### Claim 12 (depends on 8)

The FinFET device structure of claim 8, wherein the FinFET device structure is an NMOS device.

### Claim 13 (depends on 12)

The FinFET device structure of claim 12, wherein the epitaxial structure comprises crystalline silicon.

### Claim 14 (depends on 13)

The FinFET device structure of claim 13, wherein the epitaxial structure comprises phosphorus.

### Claim 15

A fin field effect transistor (FinFET) device structure comprising:
an epitaxial source/drain region located over a semiconductor substrate, the epitaxial source/drain region comprising a first surface, the first surface being substantially flat and extending along a first direction; and
a semiconductor fin extending between the epitaxial source/drain region and the semiconductor substrate and through a dielectric material, the semiconductor fin interfacing with the dielectric material, the epitaxial source/drain region having a first width greater than a second width of the semiconductor fin, the semiconductor fin comprising a second surface, wherein a line extending in a second direction through at least two points on the second surface is parallel with a major surface of the semiconductor substrate, and wherein the first direction and the second direction intersect at a first angle θ1, the first angle θ1 facing the epitaxial source/drain region being between about 90° and about 175°.

### Claim 16 (depends on 15)

The FinFET device structure of claim 15, wherein the first surface continuously extends along a first crystallographic orientation.

### Claim 17 (depends on 16)

The FinFET device structure of claim 16, wherein the first crystallographic orientation is a [111] crystallographic orientation.

### Claim 18 (depends on 15)

The FinFET device structure of claim 15, wherein the first surface and the second surface intersect each other.

### Claim 19 (depends on 15)

The FinFET device structure of claim 15, wherein the FinFET device structure is an NMOS device structure.

### Claim 20 (depends on 19)

The FinFET device structure of claim 19, wherein the epitaxial source/drain region comprises silicon and phosphorus.