# US 12,764,989 B2 · Fringe-gated castellated FET > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,764,989 B2 - Document ID: US12764989B2 - Status: Granted - Kind: B2 - Application number: 17/702,334 - Filed: 2022-03-23 - Published: 2023-09-28 - Granted: 2026-10-13 - Earliest claimed: 2022-03-23 - Assignees: Northrop Grumman Systems Corporation - Applicants: Northrop Grumman Systems Corporation - Inventors: Kevin M. Frey; Ken Nagamatsu; Josephine Chang; Robert S. Howell - Web page: https://patentgrep.com/patent/US12764989B2 ## CPC - H10D 30/4738: {having multiple donor layers} - H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT} - H10D 62/8164: {comprising only semiconductor materials (potential variation in long-range structurally-disordered materials H10D62/8163)} - H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/01: Manufacture or treatment - H10D 64/411: {for FETs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A field effect transistor, comprising: a substrate and a superlattice of stacked conducting channels on the substrate; a source and a drain spaced-apart from each other on the superlattice; alternating castellations and trenches formed in the superlattice between the source and the drain, wherein the castellations have sidewalls that cut-down through the superlattice to form the trenches and edges of the stacked conducting channels that terminate at the sidewalls; a fringe field dielectric that fills lower volumes of the trenches up to a height on the sidewalls that is higher than first edges of first conducting channels among the stacked conducting channels, such that the fringe field dielectric is adjacent to the first edges; and a gate electrode overlaying the fringe field dielectric and the castellations such that the gate electrode is not adjacent to the first edges. ## Claims ### Claim 1 A field effect transistor, comprising: a substrate and a superlattice of stacked conducting channels on the substrate; a source and a drain spaced-apart from each other on the superlattice; alternating castellations and trenches formed in the superlattice between the source and the drain, wherein the castellations have sidewalls that cut-down through the superlattice to form the trenches and edges of the stacked conducting channels that terminate at the sidewalls; a fringe field dielectric that fills lower volumes of the trenches, the fringe field dielectric having a top surface within the trenches that is lower than a height of the trenches and higher than first edges of first conducting channels among the stacked conducting channels, such that the fringe field dielectric is adjacent to the first edges; and a gate electrode overlaying the fringe field dielectric and the castellations, the gate electrode having a lower surface within the trenches that is lower than the height of the trenches and higher than the first edges such that the gate electrode is not adjacent to the first edges. ### Claim 2 (depends on 1) The field effect transistor of claim 1, wherein responsive to a gate voltage applied to the gate electrode, the gate electrode is configured to apply a fringe electric field through the fringe field dielectric to the first conducting channels to control a flow of current in the stacked conducting channels from the source to the drain. ### Claim 3 (depends on 1) The field effect transistor of claim 1, wherein: the fringe field dielectric only fills the lower volumes of the trenches, leaving upper volumes of the trenches unfilled by the fringe field dielectric; and the gate electrode fills the upper volumes of the trenches and overlays tops of the castellations to form a castellated gate electrode across the superlattice. ### Claim 4 (depends on 3) The field effect transistor of claim 3, wherein: the gate electrode that fills the upper volumes of the trenches is adjacent to second edges of second conducting channels of the stacked conducting channels that are above the first conducting channels. ### Claim 5 (depends on 1) The field effect transistor of claim 1, wherein: the fringe field dielectric fills full volumes of the trenches up to a height on the sidewalls that is flush with tops of the castellations, such that the fringe field dielectric is adjacent to the edges of all of the stacked conducting channels; and the gate electrode overlays the fringe field dielectric and tops of the castellations to form a planar gate electrode across the superlattice. ### Claim 6 (depends on 1) The field effect transistor of claim 1, wherein: the stacked conducting channels are horizontal planar channels that are stacked vertically; the sidewalls of the castellations cut-down through the superlattice from a top surface of the superlattice to bottoms of the trenches, such that the height is a vertical height; and the fringe field dielectric is horizontally adjacent to the first edges of the first conducting channels. ### Claim 7 (depends on 1) The field effect transistor of claim 1, wherein the stacked conducting channels of the superlattice include two-dimensional electron gas (2DEG) layers or two-dimensional hole gas (2DHG) layers. ### Claim 8 (depends on 1) The field effect transistor of claim 1, wherein the superlattice comprises heterostructures that form the stacked conducting channels. ### Claim 9 (depends on 8) The field effect transistor of claim 8, wherein each heterostructure includes an Aluminum Gallium Nitride (AlGaN) layer and a GaN layer. ### Claim 10 (depends on 1) The field effect transistor of claim 1, further comprising a conformal gate dielectric layer that (i) coats the superlattice and bottoms of the trenches, and (ii) underlies the fringe field dielectric and the gate electrode. ### Claim 11 (depends on 1) The field effect transistor of claim 1, wherein the field effect transistor is configured as a superlattice castellated (SLC) field effect transistor (FET) (SLCFET). ### Claim 12 A method of forming a field effect transistor, comprising: providing a substrate and forming a superlattice of stacked conducting channels on the substrate; forming a source and a drain spaced-apart from each other on the superlattice; forming alternating castellations and trenches in the superlattice between the source and the drain, the castellations having sidewalls that cut-down through the superlattice to form the trenches and edges of the stacked conducting channels that terminate at the sidewalls; forming a fringe field dielectric that fills lower volumes of the trenches, the fringe field dielectric having a top surface within the trenches that is lower than a height of the trenches and higher than first edges of first conducting channels among the stacked conducting channels, such that the fringe field dielectric is adjacent to the first edges; and forming a gate electrode overlaying the fringe field dielectric and the castellations, the gate electrode having a lower surface within the trenches that is lower than the height of the trenches and higher than the first edges such that the gate electrode is not adjacent to the first edges. ### Claim 13 (depends on 12) The method of claim 12, wherein forming the gate electrode includes forming the gate electrode such that the gate electrode is configured to, responsive to a gate voltage applied to the gate electrode, apply a fringe electric field to the first conducting channels through the fringe field dielectric to control a flow of current in the stacked conducting channels from the source to the drain. ### Claim 14 (depends on 12) The method of claim 12, wherein: forming the fringe field dielectric includes forming the fringe field dielectric to fill only the lower volumes of the trenches, leaving upper volumes of the trenches unfilled by the fringe field dielectric; and forming the gate electrode includes forming the gate electrode to fill the upper volumes of the trenches and to overlay tops of the castellations to form a castellated gate electrode across the superlattice. ### Claim 15 (depends on 14) The method of claim 14, wherein: forming the gate electrode further includes forming the gate electrode to fill the upper volumes of the trenches and to be adjacent to second edges of second conducting channels of the stacked conducting channels that are above the first conducting channels. ### Claim 16 (depends on 12) The method of claim 12, wherein: forming the fringe field dielectric includes forming the fringe field dielectric to fill full volumes of the trenches up to a height on the sidewalls that is flush with tops of the castellations, such that the fringe field dielectric is adjacent to the edges of all of the stacked conducting channels; and forming the gate electrode includes forming the gate electrode to overlay the fringe field dielectric and tops of the castellations as a planar gate electrode across the superlattice. ### Claim 17 (depends on 12) The method of claim 12, further comprising: forming the stacked conducting channels as vertically stacked, horizontal planar channels; forming the sidewalls of the castellations to cut-down through the superlattice from a top surface of the superlattice to bottoms of the trenches, such that the height is a vertical height; and forming the fringe field dielectric to be horizontally adjacent to the first edges of the first conducting channels. ### Claim 18 (depends on 12) The method of claim 12, further comprising forming the stacked conducting channels of the superlattice as two-dimensional electron gas (2DEG) layers or two-dimensional hole gas (2DHG) layers. ### Claim 19 (depends on 12) The method of claim 12, further comprising forming the stacked conducting channels of the superlattice as two-dimensional electron gas (2DEG) layers or two-dimensional hole gas (2DHG) layers. ### Claim 20 (depends on 12) The method of claim 12, further comprising forming a conformal gate dielectric layer that (i) coats the superlattice and bottoms of the trenches, and (ii) underlies the fringe field dielectric and the gate electrode.