# US 12,764,975 B2 · Three-dimensional non-volatile memory device with reduced chip size > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,764,975 B2 - Document ID: US12764975B2 - Status: Granted - Kind: B2 - Application number: 18/366,723 - Filed: 2023-08-08 - Published: 2024-02-22 - Granted: 2026-10-13 - Earliest claimed: 2022-08-17 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jooyong Park; Seungyeon Kim; Daeseok Byeon - Web page: https://patentgrep.com/patent/US12764975B2 ## CPC - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10W 90/00: Package configurations - H10W 90/792: {between multiple chips} - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A non-volatile memory device includes a first semiconductor layer including a cell area having a memory cell array and a stair area adjacent to the cell area, and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and including a row decoder. The first semiconductor layer includes a plurality of word lines stacked in the vertical direction, a layer including at least one string select line stacked on the plurality of word lines, and a plurality of first pass transistors in the stair area and on the layer including the at least one string select line, where, in the stair area, the plurality of word lines have a stepped shape, and the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder. ## Claims ### Claim 1 A non-volatile memory device comprising: a first semiconductor layer comprising a cell area that includes a memory cell array, and a stair area adjacent to the cell area; and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and comprising a row decoder, wherein the first semiconductor layer comprises: a plurality of word lines stacked in the vertical direction; a layer comprising at least one string select line stacked on the plurality of word lines; and a plurality of first pass transistors disposed in the stair area, wherein each of the plurality of first pass transistors comprises a gate and a vertical channel extending in the vertical direction, wherein the gate is at a same level as the at least one string select line relative to a substrate, wherein, in the stair area, the plurality of word lines have a stepped shape, and wherein the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder. ### Claim 2 (depends on 1) The non-volatile memory device of claim 1, wherein the at least one string select line is between the plurality of word lines and a bonding surface between the first semiconductor layer and the second semiconductor layer. ### Claim 3 (depends on 1) The non-volatile memory device of claim 1, wherein the row decoder is configured to provide a word line driving signal to the plurality of word lines through a plurality of word line driving signal lines, wherein the plurality of word line driving signal lines are in the first semiconductor layer or the second semiconductor layer. ### Claim 4 (depends on 1) The non-volatile memory device of claim 1, wherein the gate comprises a portion of the layer comprising the at least one string select line, wherein the row decoder is configured to provide a block select signal to the gate through a block select signal line, wherein the block select signal line is in the second semiconductor layer. ### Claim 5 (depends on 1) The non-volatile memory device of claim 1, wherein the second semiconductor layer comprises a second pass transistor electrically connecting the at least one string select line to the row decoder. ### Claim 6 (depends on 1) The non-volatile memory device of claim 1, wherein the layer comprising the at least one string select line comprises a first layer including a first string select line and a second layer including a second string select line that are sequentially stacked, wherein the gate of each of the plurality of first pass transistors comprises: a first gate on a portion of the first layer; and a second gate on a portion of the second layer, wherein the vertical channel extends in the vertical direction through the first gate and the second gate. ### Claim 7 (depends on 6) The non-volatile memory device of claim 6, wherein the first gate and the second gate are configured to receive a same block select signal. ### Claim 8 (depends on 6) The non-volatile memory device of claim 6, wherein the first gate is configured to receive a first block select signal and the second gate is configured to receive a second block select signal. ### Claim 9 (depends on 1) The non-volatile memory device of claim 1, wherein the cell area comprises: a plurality of vertical channel structures passing through the plurality of word lines; a plurality of string select transistor structures passing through the at least one string select line; and a plurality of pads electrically connecting the plurality of vertical channel structures to the plurality of string select transistor structures. ### Claim 10 A non-volatile memory device comprising: a first semiconductor layer comprising a memory cell array that includes a plurality of vertical channel structures; and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and comprising a row decoder, wherein the first semiconductor layer comprises: a plurality of word lines stacked in the vertical direction; a layer comprising at least one string select line stacked on the plurality of word lines; and a plurality of pass transistors, wherein each of the plurality of pass transistors comprises a gate and a vertical channel extending in the vertical direction, wherein the gate is at a same level as the at least one string select line relative to a substrate, wherein the plurality of pass transistors electrically connect the plurality of word lines to the row decoder. ### Claim 11 (depends on 10) The non-volatile memory device of claim 10, wherein the gate comprises a portion of the layer comprising the at least one string select line, wherein the first semiconductor layer further comprises a plurality of cell contact plugs electrically connecting the plurality of pass transistors to the plurality of word lines, wherein a pitch between adjacent ones of the vertical channels of the plurality of pass transistors is equal to a pitch between adjacent ones of the cell contact plugs. ### Claim 12 (depends on 10) The non-volatile memory device of claim 10, wherein the first semiconductor layer further comprises: a plurality of string select transistor structures passing through the at least one string select line; and a plurality of pads electrically connecting the plurality of vertical channel structures to the plurality of string select transistor structures. ### Claim 13 (depends on 10) The non-volatile memory device of claim 10, wherein respective widths of the plurality of word lines in the vertical direction are less than a width of the at least one string select line in the vertical direction. ### Claim 14 (depends on 10) The non-volatile memory device of claim 10, wherein the layer comprising the at least one string select line comprises a first layer including a first string select line and a second layer including a second string select line that are sequentially stacked, wherein the gate of each of the plurality of pass transistors comprises: a first gate on a portion of the first laver; and a second gate on a portion of the second layer, wherein the vertical channel extends in the vertical direction through the first gate and the second gate. ### Claim 15 (depends on 14) The non-volatile memory device of claim 14, wherein the first gate and the second gate are electrically connected to one block select transistor that is configured to provide a block select signal. ### Claim 16 (depends on 14) The non-volatile memory device of claim 14, wherein the first gate is electrically connected to a first block select transistor that is configured to provide a first block select signal, and the second gate is electrically connected to a second block select transistor that is configured to provide a second block select signal. ### Claim 17 A non-volatile memory device comprising: a first semiconductor layer comprising a memory cell array; and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and comprising a row decoder, wherein the first semiconductor layer comprises: a plurality of word lines stacked in the vertical direction; a layer comprising at least one string select line between the plurality of word lines and a bonding surface between the first semiconductor layer and the second semiconductor layer; and a plurality of first pass transistors, wherein each of the plurality of first pass transistors comprises a gate and a vertical channel extending in the vertical direction, wherein the gate is at a same level as the at least one string select line relative to a substrate, wherein the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder. ### Claim 18 (depends on 17) The non-volatile memory device of claim 17, wherein the second semiconductor layer comprises a second pass transistor electrically connecting the at least one string select line to the row decoder.