# US 12,764,974 B2 · Semiconductor package having a thick logic die

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- Number: US 12,764,974 B2
- Document ID: US12764974B2
- Status: Granted
- Kind: B2
- Application number: 18/203,666
- Filed: 2023-05-31
- Published: 2023-12-28
- Granted: 2026-10-13
- Earliest claimed: 2022-06-22
- Assignees: Mediatek Inc.
- Applicants: Mediatek Inc.
- Inventors: Ta-Jen Yu; Wen-Chin Tsai; Isabella Song; Che-Hung Kuo; Hsing-Chih Liu; Tai-Yu Chen; Shih-Chin Lin; Wen-Sung Hsu
- Web page: https://patentgrep.com/patent/US12764974B2

## CPC

- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.

## Claims

### Claim 1

A semiconductor package, comprising:
a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween, wherein the bottom substrate comprises conductive interconnect structures;
a logic die and a memory die mounted on a top surface of the bottom substrate in a side-by-side fashion, wherein the logic die has a thickness not less than 125 micrometers, wherein the memory die comprises a dynamic random access memory (DRAM) die;
a connection structure disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate; and
a sealing resin filling in the gap and sealing the logic die, the memory die, and the connection structure in the gap, wherein the logic die comprises a near-side DRAM connection circuit region that is adjacent to the DRAM die and a far-side DRAM connection circuit region that is disposed farther away from the DRAM die, wherein signals are transmitted between the DRAM die and the near-side DRAM connection circuit region through the conductive interconnect structures of the bottom substrate, and signals are transmitted between the DRAM die and the far-side DRAM connection circuit region through the top substrate and the connection structure.

### Claim 2 (depends on 1)

The semiconductor package according to claim 1, wherein the logic die has a thickness of 125-750 micrometers.

### Claim 3 (depends on 1)

The semiconductor package according to claim 1, wherein the logic die is mounted on the top surface of the bottom substrate in a flip-chip fashion.

### Claim 4 (depends on 3)

The semiconductor package according to claim 3, wherein the logic die comprises an active front side and a passive rear side, and wherein, a plurality of input/output (I/O) pads is provided on the active front side and the logic die is electrically connected to the bottom substrate through a plurality of conductive elements formed on the plurality of I/O pads, respectively.

### Claim 5 (depends on 1)

The semiconductor package according to claim 1, wherein the DRAM die comprise a Double Data Rate (DDR) DRAM die.

### Claim 6 (depends on 5)

The semiconductor package according to claim 5, wherein the DDR DRAM die comprise a Low Power DDR DRAM die.

### Claim 7 (depends on 1)

The semiconductor package according to claim 1, wherein the connection structure comprises a plurality of conductive structures and an insulating layer surrounding the plurality of conductive structures.

### Claim 8 (depends on 1)

The semiconductor package according to claim 1, wherein the logic die comprises a system-on-chip die, an application processor die, or a baseband processor die.