# US 12,764,970 B2 · Cross-point magnetoresistive memory array containing carbon-based layer and method of making the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,764,970 B2 - Document ID: US12764970B2 - Status: Granted - Kind: B2 - Application number: 18/363,542 - Filed: 2023-08-01 - Published: 2024-11-07 - Granted: 2026-10-13 - Earliest claimed: 2023-05-02 - Assignees: SanDisk Technologies LLC - Applicants: Western Digital Technologies, Inc. - Inventors: Jeffrey Lille; Jordan Katine; Tiffany Santos - Web page: https://patentgrep.com/patent/US12764970B2 ## CPC - H10B 61/10: {comprising components having two electrodes, e.g. diodes or MIM elements} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A device structure includes first electrically conductive lines that are laterally spaced apart from each other, second electrically conductive lines that are vertically spaced apart from the first electrically conductive lines and are laterally spaced apart from each other, a two-dimensional array of magnetoresistive random access memory (MRAM) pillars located between the first electrically conductive lines and the second electrically conductive lines, and each of the MRAM pillars includes a respective reference layer, a respective nonmagnetic tunnel barrier layer, and a respective free layer, and a two-dimensional array of carbon-based layers contacting surfaces of the first electrically conductive lines and surfaces of the two-dimensional array of MRAM pillars. ## Claims ### Claim 1 A device structure, comprising: first electrically conductive lines that are laterally spaced apart from each other; second electrically conductive lines that are vertically spaced apart from the first electrically conductive lines and are laterally spaced apart from each other; a two-dimensional array of magnetoresistive random access memory (MRAM) pillars located between the first electrically conductive lines and the second electrically conductive lines, wherein each of the MRAM pillars comprises a respective reference layer, a respective nonmagnetic tunnel barrier layer, and a respective free layer; a two-dimensional array of carbon-based layers contacting surfaces of the first electrically conductive lines and surfaces of the two-dimensional array of MRAM pillars, wherein the two-dimensional array of carbon-based layers underlies the two-dimensional array of MRAM pillars and contacts bottom surfaces of the two-dimensional array of MRAM pillars and contacts top surfaces of the first electrically conductive lines; and a first line-level dielectric layer embedding the first electrically conductive lines, wherein the two-dimensional array of carbon-based layers comprise bottom surface segments that contact top surface segments of the first line-level dielectric layer. ### Claim 2 (depends on 1) The device structure of claim 1, wherein at least one carbon-based layer within the two-dimensional array of carbon-based layers comprises: a central portion in contact with the top surface of a respective underlying one of the first electrically conductive lines and having a first thickness; and a peripheral portion in contact with a respective one of the top surface segments of the first line-level dielectric layer and having a second thickness that is different from the first thickness. ### Claim 3 (depends on 1) The device structure of claim 1, further comprising a two-dimensional array of metal oxide spacers laterally surrounding the two-dimensional array of MRAM pillars. ### Claim 4 (depends on 3) The device structure of claim 3, wherein at least one carbon-based layer within the two-dimensional array of carbon-based layers has a respective sidewall that is laterally recessed inward from a bottom periphery of an outer sidewall of a respective overlying metal oxide spacer within the two-dimensional array of metal oxide spacers. ### Claim 5 (depends on 3) The device structure of claim 3, wherein the two-dimensional array of metal oxide spacers is vertically spaced from and does not contact the first electrically conductive lines. ### Claim 6 (depends on 3) The device structure of claim 3, wherein the two-dimensional array of metal oxide spacers comprises oxide of metallic elements within metallic materials of the two-dimensional array of MRAM pillars, and has an inhomogeneous compositional profile along a vertical direction. ### Claim 7 (depends on 3) The device structure of claim 3, wherein the two-dimensional array of metal oxide spacers does not contact the two-dimensional array of carbon-based layers. ### Claim 8 (depends on 3) The device structure of claim 3, wherein the two-dimensional array of metal oxide spacers contacts a respective carbon-based layer of the two-dimensional array of carbon-based layers. ### Claim 9 (depends on 1) The device structure of claim 1, wherein: the two-dimensional array of carbon-based layers include carbon at an atomic percentage greater than 50% and a resistivity of less than 10 milliOhm-cm; and the two-dimensional array of carbon-based layers comprise, amorphous carbon, diamond-like carbon, a carbon-semiconductor alloy, a carbon-nitrogen alloy, a carbon-boron alloy, or a carbon-boron-nitrogen alloy. ### Claim 10 (depends on 1) The device structure of claim 1, wherein at least one carbon-based layer within the two-dimensional array of carbon-based layers comprises a respective tapered concave sidewall. ### Claim 11 (depends on 1) The device structure of claim 1, further comprising a two-dimensional array of selector pillars interposed between the two-dimensional array of MRAM pillars and the second electrically conductive lines. ### Claim 12 (depends on 1) A computer system comprising a computer memory containing the device structure of claim 1. ### Claim 13 A device structure, comprising: first electrically conductive lines that are laterally spaced apart from each other; second electrically conductive lines that are vertically spaced apart from the first electrically conductive lines and are laterally spaced apart from each other; a two-dimensional array of magnetoresistive random access memory (MRAM) pillars located between the first electrically conductive lines and the second electrically conductive lines, wherein each of the MRAM pillars comprises a respective reference layer, a respective nonmagnetic tunnel barrier layer, and a respective free layer; a two-dimensional array of carbon-based layers contacting surfaces of the first electrically conductive lines and surfaces of the two-dimensional array of MRAM pillars; and a two-dimensional array of metal oxide spacers laterally surrounding the two-dimensional array of MRAM pillars, wherein at least one carbon-based layer within the two-dimensional array of carbon-based layers has a respective sidewall that is laterally recessed inward from a bottom periphery of an outer sidewall of a respective overlying metal oxide spacer within the two-dimensional array of metal oxide spacers. ### Claim 14 A device structure, comprising: first electrically conductive lines that are laterally spaced apart from each other; second electrically conductive lines that are vertically spaced apart from the first electrically conductive lines and are laterally spaced apart from each other; a two-dimensional array of magnetoresistive random access memory (MRAM) pillars located between the first electrically conductive lines and the second electrically conductive lines, wherein each of the MRAM pillars comprises a respective reference layer, a respective nonmagnetic tunnel barrier layer, and a respective free layer; a two-dimensional array of carbon-based layers contacting surfaces of the first electrically conductive lines and surfaces of the two-dimensional array of MRAM pillars; and a two-dimensional array of metal oxide spacers laterally surrounding the two-dimensional array of MRAM pillars, wherein the two-dimensional array of metal oxide spacers comprises oxide of metallic elements within metallic materials of the two-dimensional array of MRAM pillars, and has an inhomogeneous compositional profile along a vertical direction. ### Claim 15 A device structure, comprising: first electrically conductive lines that are laterally spaced apart from each other; second electrically conductive lines that are vertically spaced apart from the first electrically conductive lines and are laterally spaced apart from each other; a two-dimensional array of magnetoresistive random access memory (MRAM) pillars located between the first electrically conductive lines and the second electrically conductive lines, wherein each of the MRAM pillars comprises a respective reference layer, a respective nonmagnetic tunnel barrier layer, and a respective free layer; a two-dimensional array of carbon-based layers contacting surfaces of the first electrically conductive lines and surfaces of the two-dimensional array of MRAM pillars; and a two-dimensional array of metal oxide spacers laterally surrounding the two-dimensional array of MRAM pillars, wherein the two-dimensional array of metal oxide spacers does not contact the two-dimensional array of carbon-based layers.