# US 12,764,964 B2 · Three-dimensional ferroelectric memory device

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- Number: US 12,764,964 B2
- Document ID: US12764964B2
- Status: Granted
- Kind: B2
- Application number: 18/491,161
- Filed: 2023-10-20
- Published: 2024-05-23
- Granted: 2026-10-13
- Earliest claimed: 2022-11-21
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Seunggeol Nam; Jinseong Heo; Hyunjae Lee; Dukhyun Choe
- Web page: https://patentgrep.com/patent/US12764964B2

## CPC

- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 51/10: characterised by the top-view layout
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/689: {having ferroelectric layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided is a three-dimensional (3D) ferroelectric memory device. The 3D ferroelectric memory device includes a substrate, a plurality of insulating layers stacked on the substrate, a plurality of gate electrodes between the plurality of insulating layers, a plurality of gate insulating layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of gate insulating layers, a ferroelectric layer in contact with the plurality of intermediate electrodes and the plurality of insulating layers, and a channel layer in contact with the ferroelectric layer.

## Claims

### Claim 1

A three-dimensional (3D) ferroelectric memory device comprising:
a substrate;
a plurality of insulating layers stacked on an upper surface of the substrate;
a plurality of gate electrodes between the plurality of insulating layers;
a plurality of gate insulating layers on corresponding side surfaces of the plurality of gate electrodes;
a ferroelectric layer on side surfaces of the plurality of insulating layers;
a plurality of intermediate electrodes between the plurality of gate insulating layers and the ferroelectric layer; and
a channel layer on the ferroelectric layer,
wherein the plurality of gate insulating layers are between the plurality of gate electrodes and the plurality of intermediate electrodes, and
wherein the ferroelectric layer is between the plurality of intermediate electrodes and the channel layer.

### Claim 2 (depends on 1)

The 3D ferroelectric memory device of claim 1, wherein each of the plurality of intermediate electrodes is configured to include a charge of a first polarity.

### Claim 3 (depends on 1)

The 3D ferroelectric memory device of claim 1, wherein in a cross-sectional view, the plurality of gate electrodes are stacked in a direction perpendicular to the upper surface of the substrate, and each of the plurality of gate electrodes extends in a direction parallel to the upper surface of the substrate.

### Claim 4 (depends on 3)

The 3D ferroelectric memory device of claim 3, wherein each of the plurality of gate electrodes is electrically connected to a word line, and each of the plurality of intermediate electrodes are configured to be a floating electrode.

### Claim 5 (depends on 1)

The 3D ferroelectric memory device of claim 1, wherein the plurality of intermediate electrodes extend to protrude from the side surfaces of the plurality of insulating layers in a first direction parallel to the upper surface of the substrate.

### Claim 6 (depends on 5)

The 3D ferroelectric memory device of claim 5, wherein the ferroelectric layer and the channel layer each have a protruding shape corresponding to a protruding portion of the plurality of intermediate electrodes.

### Claim 7 (depends on 5)

The 3D ferroelectric memory device of claim 5, wherein
the plurality of gate insulating layers are respectively on an upper surface, a lower surface, and the side surface of corresponding gate electrodes of the plurality of gate electrodes,
the upper surface and the lower surfaces of the corresponding gate electrodes are parallel to the upper surface of the substrate, and
the side surface of the corresponding gate electrodes are perpendicular to an upper surface the substrate.

### Claim 8 (depends on 5)

The 3D ferroelectric memory device of claim 5, wherein the plurality of gate insulating layers are respectively on one side surface of corresponding gate electrodes of the plurality of gate electrodes.

### Claim 9 (depends on 5)

The 3D ferroelectric memory device of claim 5, wherein a source electrode and a drain electrode are respectively on both sides of the channel layer in a second direction that is parallel to the substrate and perpendicular to the first direction.

### Claim 10 (depends on 9)

The 3D ferroelectric memory device of claim 9, wherein the source electrode is electrically connected to a corresponding source line, and the drain electrode is electrically connected to a corresponding bit line.

### Claim 11 (depends on 1)

The 3D ferroelectric memory device of claim 1, wherein, in a cross-sectional view, the plurality of intermediate electrodes extend towards the side surfaces of the plurality of insulating layers in a first direction parallel to the upper surface the substrate.

### Claim 12 (depends on 11)

The 3D ferroelectric memory device of claim 11, wherein
the plurality of gate insulating layers are respectively on an upper surface, a lower surface, and the side surface of corresponding gate electrodes of the plurality of gate electrodes,
the upper surface and the lower surfaces of the corresponding gate electrodes are parallel to the upper surface of the substrate, and
the side surface of the corresponding gate electrodes are perpendicular to the upper surface of the substrate.

### Claim 13 (depends on 11)

The 3D ferroelectric memory device of claim 11, wherein the plurality of gate insulating layers are respectively on the side surface of corresponding gate electrodes of the plurality of gate electrodes.

### Claim 14 (depends on 1)

The 3D ferroelectric memory device of claim 1, wherein each of the plurality of gate electrodes and each of the plurality of intermediate electrodes independently include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, or polysilicon.

### Claim 15 (depends on 1)

The 3D ferroelectric memory device of claim 1, wherein the plurality of insulating layers comprise at least one of SiO, SiOC, SiON, or SiN.

### Claim 16 (depends on 1)

The 3D ferroelectric memory device of claim 1, wherein the ferroelectric layer comprise at least one of a ferroelectric fluorite-based material, a ferroelectric nitride-based material, or a ferroelectric perovskite.

### Claim 17 (depends on 1)

The 3D ferroelectric memory device of claim 1, wherein the plurality of gate insulating layers comprise at least one of SiO, SiN, AlO, HfO, or ZrO.

### Claim 18 (depends on 17)

The 3D ferroelectric memory device of claim 17, wherein the channel layer is provided to correspond with the plurality of gate electrodes.

### Claim 19 (depends on 18)

The 3D ferroelectric memory device of claim 18, wherein the channel layer comprises at least one of a Group IV semiconductor, a Group III-V semiconductor, an oxide semiconductor, a nitride semiconductor, a nitrogen oxide semiconductor, a two-dimensional (2D) semiconductor material, quantum dots, or an organic semiconductor.

### Claim 20 (depends on 1)

The 3D ferroelectric memory device of claim 1, wherein the channel layer extends in a direction perpendicular to the upper surface of the substrate.