Three-dimensional memory device and enhanced electronic system

An integrated circuit device, comprising:

• a semiconductor substrate comprising a memory cell area and a connection area;
• a gate stack comprising a plurality of word lines and a plurality of insulating layers, the plurality of word lines and the plurality of insulating layers extending in a first direction of a main surface of the semiconductor substrate and being alternately stacked in a second direction perpendicular to the main surface of the semiconductor substrate;
• a word line cut region passing through the plurality of word lines in the memory cell area and the connection area and extending in a third direction;
• a plurality of first channel structures disposed on the memory cell area and each of the plurality of first channel structures extending in the second direction and passing through the gate stack in the second direction;
• at least one string select line disposed on the gate stack in the memory cell area;
• a plurality of second channel structures passing through the at least one string select line and each of the plurality of second channel structures extending in the second direction;
• and
• a string select line cut region passing through the at least one string select line and extending in the third direction,
• wherein a portion of the at least one string select line is disposed as a cover structure overlapping the word line cut region,
• wherein the word line cut region has a shape of which a first horizontal width decreases as a distance from the main surface of the semiconductor substrate decreases, and
• wherein the cover structure disposed on the word line cut region extends in the third direction and has a shape of which a second horizontal width increases as the distance from the main surface of the semiconductor substrate decreases.