Semiconductor memory device and method for forming the same
AssigneeWinbond Electronics Corp.
InventorFrederick Chen
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a plurality of nanowires vertically stacked over a substrate, and a plurality of memory films wrapping around the plurality of nanowires, respectively. Each of the memory films includes a first oxide layer, a nitride layer and a second oxide layer sequentially formed over the corresponding nanowire. The semiconductor memory device also includes a gate electrode layer surrounding the plurality of memory films, and an isolation structure encapsulating the gate electrode layer. The isolation structure is in direct contact with the gate electrode layer and the nitride layers of the memory films.
Claims19
A semiconductor memory device, comprising:
- a plurality of nanowires vertically stacked over a substrate;
- a plurality of memory films, wherein each memory film of the plurality of memory films wraps around a corresponding nanowire of the plurality of nanowires and includes at least two dielectric layers;
- a gate electrode layer surrounding the plurality of memory films;
- an isolation structure encapsulating the gate electrode layer, wherein the isolation structure is in direct contact with the gate electrode layer and the at least two dielectric layers of the memory films;
- a plurality of first conductive lines vertically stacked over the substrate and electrically coupled to first ends of the plurality of nanowires, respectively;
- and
- a plurality of second conductive lines vertically stacked over the substrate and electrically coupled to second ends of the plurality of nanowires, respectively.
A semiconductor memory device, comprising:
- a first column of memory transistors stacked in a vertical direction, wherein each of the memory transistors in the first column comprises at least two nanowires, and the nanowires of the memory transistors are stacked in respective levels;
- a second column of drain lines stacked in the respective levels in the vertical direction, wherein the drain lines in the second column are divided into groups, each of the groups of drain lines comprises at least two drain lines that are electrically coupled to the at least two nanowires of a corresponding memory transistor;
- and
- a plurality of conductive vias corresponding to the groups of drain lines, respectively, wherein each of the conductive vias penetrates through the at least two drain lines in a corresponding one of the groups of drain lines, and the at least two drain lines in each group are electrically connected through a corresponding one of the conductive vias.
Dependencies are inferred from the claim text.