# US 12,764,940 B2 · Dynamic random access memory with buried bit line and method for forming the same

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- Number: US 12,764,940 B2
- Document ID: US12764940B2
- Status: Granted
- Kind: B2
- Application number: 18/338,026
- Filed: 2023-06-20
- Published: 2024-01-11
- Granted: 2026-10-13
- Earliest claimed: 2022-07-06
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Ying-Chu Yen
- Web page: https://patentgrep.com/patent/US12764940B2

## CPC

- H10B 12/482: {Bit lines}
- H10B 12/038: {the capacitor being in a trench in the substrate}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/485: {Bit line contacts}
- H10B 12/488: {Word lines}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for forming a Dynamic Random Access Memory (DRAM) includes forming an isolation structure in a substrate to define an active region. The method also includes forming a bit line trench in the active region to divide two active pillars. The method also includes forming a buried bit line in the bit line trench. The method also includes forming an insulating material over the bit line in the bit line trench. The top surface of the insulating material is lower than the top surface of the substrate. A trench is formed over the insulating material. The method also includes forming a shallow recess on the sidewalls of each of the active pillars exposed by the trench to make that each of the active pillars has a neck channel region. The method also includes forming a buried word line in the shallow recess.

## Claims

### Claim 1

A DRAM, comprising:
a substrate comprising an active region, wherein the active region comprises two active pillars with neck channel regions, and a shallow recess is formed on surfaces of each of the neck channel regions;
a buried bit line between the active pillars, and a top surface of the buried bit line is lower than a top surface of the substrate;
an insulating structure over the buried bit line to separate the active pillars of the active regions an isolation structure to define the active region, and the isolation structure has a width less than a width of the insulating structure; and
a plurality of buried word lines, wherein each of the buried word lines is contained in the shallow recess to surround the neck channel region of each of the active pillars, and the insulating structure is between the buried word lines,
wherein the shallow recess is a concave recess defined in a sidewall of the neck channel region.

### Claim 2 (depends on 1)

The DRAM as claimed in claim 1, wherein the buried word line comprises:
a gate dielectric layer formed on surfaces of the neck channel region of each of the active pillars;
a barrier layer formed over the gate dielectric layer; and
a gate electrode layer formed over the barrier layer.

### Claim 3 (depends on 2)

The DRAM as claimed in claim 2, wherein the gate electrode layer is embedded in a recess formed on a surface of the barrier layer.

### Claim 4 (depends on 2)

The DRAM as claimed in claim 2, wherein a sidewall of the gate electrode layer interfaces with the insulating structure.

### Claim 5 (depends on 2)

The DRAM as claimed in claim 2, wherein distinct portions of a top surface of the gate electrode layer are respectively in direct contact with the insulating structure and the barrier layer.

### Claim 6 (depends on 2)

The DRAM as claimed in claim 2, wherein the gate dielectric layer has a U-shaped cross-sectional profile.

### Claim 7 (depends on 2)

The DRAM as claimed in claim 2, wherein, in a cross-sectional view, the barrier layers located on opposite sides of the neck channel region each have a U-shaped profile, and openings of the U-shaped profiles face away from each other.

### Claim 8 (depends on 1)

The DRAM as claimed in claim 1, further comprising:
a bit line contact structure disposed between the buried bit line and the substrate;
a capacitor contact structure formed over top portions of each of the active pillars; and
a capacitor formed over the capacitor contact structure.

### Claim 9 (depends on 1)

The DRAM as claimed in claim 1, wherein the buried bit line has a bending pattern, and a portion of the buried bit line is parallel to the active region, and another portion of the buried bit line overlaps the active region, such that the capacitor contact structure is on opposite sides of the other portion of the buried bit line.

### Claim 10 (depends on 1)

The DRAM as claimed in claim 1, wherein the active region has a rounded corner.